# US 2010/0164586 A1 · Progamable control clock circuit for arrays > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2010/0164586 A1 - Document ID: US20100164586A1 - Status: Published application - Kind: A1 - Application number: 12/345,758 - Filed: 2008-12-30 - Published: 2010-07-01 - Earliest claimed: 2008-12-30 - Assignees: International Business Machines Corporation - Inventors: Rolf Sautter; Michael Ju Hyeok Lee; Yuen Hung Chan; Juergen Pille - Web page: https://patentgrep.com/patent/US20100164586A1 ## CPC - G06F 1/04: Generating or distributing clock signals or signals derived directly therefrom - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A programmable clock control circuit includes a base block, a chop block, and a pulse width variation block coupled between the chop block and the base block that receives the chop block output and provides a pulse width variation output to the base block. The pulse width variation block is programmable to vary the chop block output to provide at least three different output pulse widths. The circuit also includes a clock delay block coupled an output of the base block to delay the output pulse and having a clock signal output. ## Claims ### Claim 1 A programmable clock control circuit, the circuit comprising: a base block configured to control operation of the programmable clock control circuit and coupled to a negative clock signal; a chop block configured to control the width of an output clock signal of the programmable clock control circuit and having a chop block output; a pulse width variation block coupled between the chop block and the base block, the pulse width variation block receiving the chop block output and providing a pulse width variation output to the base block, the pulse width variation being programmable to vary the chop block output to provide at least three different output pulse widths; a clock delay block coupled an output of the base block to delay the output pulse and having a clock signal output; and a clock driver circuit coupled to the clock delay block and configured to receive the clock signal output and to produce the output clock signal. ### Claim 2 (depends on 1) The circuit of claim 1, wherein the pulse width variation block includes three control inputs. ### Claim 3 (depends on 2) The circuit of claim 2, wherein the control inputs control the operation of the pulse width variation block to alter the chop block output. ### Claim 4 (depends on 2) The circuit of claim 2, wherein the pulse width variation block comprises: an NFET stack coupled to the three control inputs. ### Claim 5 (depends on 4) The circuit of claim 4, wherein each control input is coupled, at least in part, to the NFET stack through an NFET. ### Claim 6 (depends on 1) The circuit of claim 1, wherein the clock delay block includes at least three different delay settings. ### Claim 7 (depends on 6) The circuit of claim 6, wherein the clock delay block includes two delay control inputs. ### Claim 8 (depends on 6) The circuit of claim 6, wherein the clock delay block includes a plurality of delay structures. ### Claim 9 (depends on 6) The circuit of claim 6, wherein in the event that a first of the delay control inputs is low and the second of the delay control inputs is low, a first delay structure delays the output pulse a first delay amount. ### Claim 10 (depends on 9) The circuit of claim 9, wherein in the event that a first of the delay control inputs is low and the second of the delay control inputs is high, the first delay structure and a second delay structure delay the output pulse a second delay amount greater than the first delay amount. ### Claim 11 (depends on 10) The circuit of claim 10, wherein in the event that a first of the delay control inputs is high, the first delay structure, the second delay structure delay and a third delay structure delay the output pulse a third delay amount greater than the second delay amount. ### Claim 12 (depends on 11) The circuit of claim 11, wherein the first delay structure includes one inverter, the second delay structure includes three inverters and the third delay structure includes five inverters. ### Claim 13 (depends on 12) The circuit of claim 12, wherein one or more of the more of the inverters is formed by an NFET/PFET pair. ### Claim 14 A programmable clock control circuit, the circuit comprising: a clock driver circuit configured to provide an output clock signal; a base block configured to control operation of the programmable clock control circuit; and a clock delay block between the base block and the clock driver circuit configured to receive a clocking signal from the base block and delay it an adjustable amount before the signal is transmitted to the clock driver circuit, the clock delay block including two delay control inputs. ### Claim 15 (depends on 14) The circuit of claim 14, wherein the clock delay block includes a plurality of delay structures. ### Claim 16 (depends on 15) The circuit of claim 15, wherein, in the event that a first of the delay control inputs is low and the second of the delay control inputs is low, a first delay structure delays the output pulse a first delay amount, in the event that a first of the delay control inputs is low and the second of the delay control inputs is high, the first delay structure and a second delay structure delay the output pulse a second delay amount greater than the first delay amount, and in the event that a first of the delay control inputs is high, the first delay structure, the second delay structure delay and a third delay structure delay the output pulse a third delay amount greater than the second delay amount. ### Claim 17 (depends on 16) The circuit of claim 16, wherein the first delay structure includes one inverter, the second delay structure includes three inverters and the third delay structure includes five inverters. ### Claim 18 (depends on 17) The circuit of claim 17, wherein one or more of the more of the inverters is formed by an NFET/PFET pair.