# US 2010/0164584 A1 · Timing Generator

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- Number: US 2010/0164584 A1
- Document ID: US20100164584A1
- Status: Published application
- Kind: A1
- Application number: 12/344,424
- Filed: 2008-12-26
- Published: 2010-07-01
- Earliest claimed: 2008-12-26
- Assignees: Advantest Corporatiion, a Japanese Corporation
- Inventors: Daisuke Watanabe; Toshiyuki Okayasu
- Web page: https://patentgrep.com/patent/US20100164584A1

## CPC

- G01R 31/31725: {Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937)}
- G01R 31/3016: {Delay or race condition test, e.g. race hazard test}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A delay setting data generator generates delay setting data based on rate data. A variable delay circuit delays the test pattern data by a delay time determined by the delay setting data with reference to a predefined unit amount of delay. First rate data designates the period of the test pattern data with a precision determined by the unit amount of delay. Second rate data designates the period of the test pattern data with a precision higher than that determined by the unit amount of delay. The delay setting data generator outputs a first value and a second value in a time division manner at a ratio determined by the second rate data, the first and second values being determined by the first rate data.

## Claims

### Claim 1

A timing generator adapted to receive test pattern data to be supplied to a device under test and rate data for setting the period of the test pattern data, and control the timing of outputting the test pattern data to the device under test according to the rate data, comprising:
a delay setting data generator operative to receive the rate data and generate delay setting data; and
a variable delay circuit operative to delay the test pattern data by a delay time determined by the delay setting data with reference to a predefined unit amount of delay,
wherein
the rate data comprises first rate data designating the period of the test pattern data with a precision determined by the unit amount of delay and second rate data designating the period of the test pattern data with a precision higher than that determined by the unit amount of delay, and
the delay setting data generator is operative to output a first value and a second value in a time division manner at a ratio determined by the second rate data, the first value being determined by the first rate data and the second value being determined by the first rate data and different from the first value.

### Claim 2 (depends on 1)

The timing generator according to claim 1, wherein
the delay setting data generator generates a serial data sequence in which 0 s and 1 s occur at frequencies determined by the second rate data, adds the bits of the serial data sequence to the first rate data or subtracts the bits of the serial data sequence from the first rate data, and outputs the resultant data as the delay setting data.

### Claim 3 (depends on 2)

The timing generator according to claim 2, wherein
the delay setting data generator includes a pseudorandom data generator capable of controlling the mark-to-space ratio according to the second rate data, and uses the output from the pseudorandom data generator as the serial data sequence.

### Claim 4 (depends on 1)

The timing generator according to claim 1, wherein
the delay setting data generator includes an nth-order ΔΣ modulator for subjecting the second rate data to ΔΣ modulation, where n is a natural number, adds the sequence of ith-order bits of the second rate data thus modulated to the ith bits in the lower group of bits in the first rate data, respectively, or subtracts the ith-order bits from the ith bits, respectively, where 1≦i≦n, and outputs the resultant data as the delay setting data.

### Claim 5 (depends on 1)

The timing generator according to claim 1, wherein
the delay setting data generator further comprises an integrator operable to integrate the first rate data at intervals defined by a first clock,
given that division of the data output from the integrator by a reference value determined by the period of the first clock produces a quotient α and a remainder β, where α and β denote integers,
the delay setting data generator sets the first value and the second value to values determined by the remainder β, and
the timing generator delays the test pattern data by a total of α periods of the first clock.

### Claim 6 (depends on 1)

A test apparatus comprising:
a pattern generator operative to produce test pattern data to be supplied to a device under test; and
the timing generator according to claim 1 operable to control the timing of outputting the test pattern data to the device under test according to rate data.

### Claim 7

A method of controlling a test rate at which test pattern data is output to a device under test, based on rate data for setting the period of the test pattern data to be supplied to the device under test, wherein
the rate data comprises first rate data designating the period of the test pattern data with a precision determined by the unit amount of delay and second rate data designating the period of the test pattern data with a precision higher than that determined by the unit amount of delay, and
the method comprises:
setting delay setting data to be a first value and a second value in a time division manner at a ratio determined by the second rate data, the first value being determined by the first rate data and the second value being determined by the first rate data and different from the first value; and
delaying the test pattern data by a delay time determined by the delay setting data with reference to a predefined unit amount of delay.

### Claim 8 (depends on 7)

The method according to claim 7, wherein
the setting of the delay setting data comprises:
generating a serial data sequence in which 0 s and 1 s occur at frequencies determined by the second rate data; and
adding the bits of the serial data sequence to the first rate data or subtracting the bits of the serial data sequence from the first rate data, so as to set the delay setting data to be the data resulting from addition or subtraction.

### Claim 9 (depends on 7)

The method according to claim 7, wherein
the setting of the delay setting data comprises:
subjecting the second rate data to n-th order ΔΣ modulation, where n is a natural number, and
adding the sequence of ith-order bits of the second rate data thus modulated to the ith bits of the first rate data, respectively, or subtracts the ith-order bits from the i-th bits, respectively, where 1≦i≦n.