# US 2010/0164580 A1 · High speed clock signal duty cycle adjustment > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2010/0164580 A1 - Document ID: US20100164580A1 - Status: Published application - Kind: A1 - Application number: 12/347,469 - Filed: 2008-12-31 - Published: 2010-07-01 - Earliest claimed: 2008-12-31 - Assignees: International Business Machines Corporation; IBM Corporation - Inventors: David William Boerstler; Steven Mark Clements; Jieming Qi - Web page: https://patentgrep.com/patent/US20100164580A1 ## CPC - H03K 5/1565: {the output pulses having a constant duty cycle} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A clock signal duty cycle adjustment circuit includes a duty cycle correction circuit that receives a clock input signal that may need duty cycle correction. The duty cycle correction circuit may derive first and second differential clock signals from the clock input signal. The first and second differential clock signals may exhibit respective voltage offsets. The duty cycle correction circuit includes a voltage offset shift circuit that may shift the voltage offset that one of the first and second differential clock signals exhibits to adjust the effective duty cycle of a clock output signal. The duty cycle adjustment circuit derives the clock output signal from the voltage offset adjusted first and second differential clock signals in response to a duty cycle error signal. ## Claims ### Claim 1 A method of adjusting the duty cycle of a signal, the method comprising: generating, by a clock signal source circuit, a clock input signal that includes true and complement clock signals; receiving, by a duty cycle correction circuit, the clock input signal; deriving from the clock input signal, by the duty cycle correction circuit, first and second differential clock signals corresponding to the true and complement clock signals, respectively, the first and second differential clock signals exhibiting respective voltage offsets; and shifting, by the duty cycle correction circuit, the voltage offset of one of the first and second differential clock signals in response to a duty cycle exhibited by a clock output signal derived from the first and second differential clock signals. ### Claim 2 (depends on 1) The method of claim 1, further comprising detecting, by an error detection circuit, a duty cycle error in the clock output signal. ### Claim 3 (depends on 1) The method of claim 1, wherein the shifting step shifts the voltage offset of one of the first and second differential clock signals in response to a duty cycle error signal, thus providing a voltage offset shifted differential clock signal and a voltage offset un-shifted differential clock signal. ### Claim 4 (depends on 3) The method of claim 3, wherein the detecting step includes low pass filtering, by a low pass filter in the error detection circuit, the clock output signal to generate the duty cycle error signal. ### Claim 5 (depends on 4) The method of claim 4, further comprising generating, by the low pass filter, a DC voltage error signal that exhibits a voltage proportional to the duty cycle of the clock output signal. ### Claim 6 (depends on 3) The method of claim 3, wherein the detecting step includes determining, by the error detection circuit, times when the voltage offset shifted differential clock signal intersects with the voltage offset un-shifted differential clock signal. ### Claim 7 (depends on 1) The method of claim 1, further comprising providing the first and second differential clock signals to first and second nodes, respectively, of the duty cycle correction circuit, the duty cycle correction circuit pulling one of the first and second nodes down to shift the voltage offset of one of the first and second differential clock signals to affect the duty cycle of the clock output signal. ### Claim 8 A duty cycle adjustment circuit, comprising: a clock input that receives a clock input signal that includes true and complement clock signals; a duty cycle correction circuit, coupled to the clock input, that derives from the clock input signal first and second differential clock signals corresponding to the true and complement clock signals, respectively, the first and second differential clock signals exhibiting respective voltage offsets; the duty cycle correction circuit including a voltage offset shift circuit that shifts the voltage offset exhibited by one of the first and second differential clock signals in response to a duty cycle exhibited by a clock output signal derived from the first and second differential clock signals, the duty cycle correction circuit thus providing a duty cycle adjusted clock output signal. ### Claim 9 (depends on 8) The duty cycle adjustment circuit of claim 8, further comprising an error detection circuit, coupled to the duty cycle correction circuit to receive the clock output signal and detect duty cycle error in the clock output signal. ### Claim 10 (depends on 8) The duty cycle adjustment circuit of claim 8, wherein the duty cycle correction circuit shifts the voltage offset of one of the first and second differential clock signals in response to a duty cycle error signal, thus providing a voltage offset shifted differential clock signal and a voltage offset un-shifted differential clock signal. ### Claim 11 (depends on 10) The duty cycle adjustment circuit of claim 10, wherein the error detection circuit includes a low pass filter that filters the clock output signal to generate the duty cycle error signal. ### Claim 12 (depends on 11) The duty cycle adjustment circuit of claim 11, wherein the low pass filter generates a DC voltage error signal that exhibits a voltage proportional to the duty cycle of the clock output signal. ### Claim 13 (depends on 10) The duty cycle adjustment circuit of claim 10, wherein the error detection circuit determines times when the voltage offset shifted differential clock signal intersects with the voltage offset un-shifted differential clock signal. ### Claim 14 (depends on 8) The duty cycle adjustment circuit of claim 8, wherein the duty cycle correction circuit includes first and second nodes to which the first and second differential clock signals are provided, respectively, the duty cycle correction circuit pulling one of the first and second nodes down to shift the voltage offset of one of the first and second differential clock signals to affect the duty cycle of the clock output signal. ### Claim 15 An information handling system (IHS), comprising a memory, a processor coupled to the memory, the processor including a duty cycle adjustment circuit, the duty cycle adjustment circuit including: a clock input that receives a clock input signal that includes true and complement clock signals; a duty cycle correction circuit, coupled to the clock input, that derives from the clock input signal first and second differential clock signals corresponding to the true and complement clock signals, respectively, the first and second differential clock signals exhibiting respective voltage offsets; the duty cycle correction circuit including a voltage offset shift circuit that shifts the voltage offset exhibited by one of the first and second differential clock signals in response to a duty cycle exhibited by a clock output signal derived from the first and second differential clock signals, the duty cycle correction circuit thus providing a duty cycle adjusted clock output signal. ### Claim 16 (depends on 15) The IHS of claim 15, further comprising an error detection circuit, coupled to the duty cycle correction circuit to receive the clock output signal and detect duty cycle error in the clock output signal. ### Claim 17 (depends on 15) The IHS of claim 15, wherein the duty cycle correction circuit shifts the voltage offset of one of the first and second differential clock signals in response to a duty cycle error signal, thus providing a voltage offset shifted differential clock signal and a voltage offset un-shifted differential clock signal. ### Claim 18 (depends on 17) The IHS of claim 17, wherein the error detection circuit includes a low pass filter that filters the clock output signal to generate the duty cycle error signal. ### Claim 19 (depends on 18) The IHS of claim 18, wherein the low pass filter generates a DC voltage error signal that exhibits a voltage proportional to the duty cycle of the clock output signal. ### Claim 20 (depends on 17) The IHS of claim 17, wherein the error detection circuit determines times when the voltage offset shifted differential clock signal intersects with the voltage offset un-shifted differential clock signal. ### Claim 21 (depends on 15) The IHS of claim 15, wherein the duty cycle correction circuit includes first and second nodes to which the first and second differential clock signals are provided, respectively, the duty cycle correction circuit pulling one of the first and second nodes down to shift the voltage offset of one of the first and second differential clock signals to affect the duty cycle of the clock output signal.