# US 2010/0164574 A1 · Simplified, extendable, edge-based watchdog for dll

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- Number: US 2010/0164574 A1
- Document ID: US20100164574A1
- Status: Published application
- Kind: A1
- Application number: 12/624,047
- Filed: 2009-11-23
- Published: 2010-07-01
- Earliest claimed: 2008-11-24
- Assignees: Texas Instruments Incorporated
- Inventors: Samarth S. Modi; Nitin Agarwal; Mrityunjay Kr Baranwal
- Web page: https://patentgrep.com/patent/US20100164574A1

## CPC

- H03L 7/0816: {the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input}
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

A delay locked loop (DLL) is provided. Within this DLL is a watchdog circuit that determines whether harmonic lock is present. Based on this measurement, the watchdog circuit can provide adjustments to the DLL so as to change the length of the delay of the delay line to bring it within a predetermined range.

## Claims

### Claim 1

An apparatus comprising:
a phase detector (PD) that receives a clock signal;
a charge pump that is coupled to the phase detector;
a loop filter that is coupled to the charge pump;
a delay line having a plurality of taps and a delay, wherein the delay line receives the clock signal, and wherein the delay line is coupled to the loop filter and the PD;
a watchdog circuit that is coupled to the delay line so as to receive a first signal from a first tap of the plurality of taps and a second signal from a second tap of the plurality of taps, that receives the clock signal, and that is coupled to at least one of the charge pump and PD, wherein the watchdog circuit compares a rising edge from the first signal to a corresponding rising edge from the second signal, and wherein, when the rising edge from the first signal occurs before the corresponding rising edge from the second signal, the watchdog circuit determines that the delay of the delay line is within a predetermined range, and wherein, when the when the rising edge from the first signal occurs after the corresponding rising edge from the second signal, the watchdog circuit adjusts the charge pump so as to adjust the delay to be within the predetermined range.

### Claim 2 (depends on 2)

The apparatus of claim 2, wherein the delay line further comprises a plurality of buffers that are coupled in series with one another and that are each coupled to the loop filter.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the predetermined range is the range of the phase detector.

### Claim 4 (depends on 2)

The apparatus of claim 2, wherein the watchdog circuit calculates whether a harmonic lock condition exists and provides a harmonic detect signal to at least one of the charge pump and PD that indicates whether the harmonic lock condition exists.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the watchdog further comprises a plurality of watchdog circuits coupled in parallel with one another to determine whether higher order harmonic lock conditions are present.

### Claim 6

An apparatus comprising:
a delay-locked loop (DLL) that receives a clock signal and that generates a plurality of delay signals, wherein the DLL has a delay;
a watchdog circuit that is coupled to the DLL so as to receive a first delay signal from the plurality of delay signals and a second delay signal from the plurality of delay signals and that receives the clock signal, wherein the watchdog circuit compares a rising edge from the first delay signal to a corresponding rising edge from the second delay signal, and wherein, when the rising edge from the first signal occurs before the corresponding rising edge from the second signal, the watchdog circuit determines that the delay of DLL is within a predetermined range, and wherein, when the when the rising edge from the first signal occurs after the corresponding rising edge from the second signal, the watchdog circuit adjusts the DLL so as to adjust the delay to be within the predetermined range.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein the predetermined range is a phase detector range.

### Claim 8 (depends on 6)

The apparatus of claim 6, wherein the watchdog circuit calculates whether a harmonic lock condition exists and provides a harmonic detect signal to the DLL that indicates whether the harmonic lock condition exists.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the watchdog further comprises a plurality of watchdog circuits coupled in parallel with one another to determine whether higher order harmonic lock conditions are present.

### Claim 10

A method comprising:
receiving a rising edge from a clock signal;
receiving a first corresponding rising edge from a first tap in a delay line of a DLL;
receiving a second corresponding rising edge from a second tap of the delay line of the DLL, wherein the first and corresponding rising edges correspond to the rising edge of the clock signal;
if the second corresponding rising edge occurs before the first corresponding rising edge, indicating a harmonic lock condition; and
adjusting a charge pump of the DLL so that the first corresponding clock edge occurs before the second corresponding clock edge

### Claim 11 (depends on 10)

The method of claim 10, wherein the method further comprises the step of indicating the harmonic lock condition if either of the first and second corresponding rising edges from the first and second taps, respectively, occurs before the rising edge of the clock signal.