# US 2010/0164568 A1 · Low power variable delay circuit

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- Number: US 2010/0164568 A1
- Document ID: US20100164568A1
- Status: Published application
- Kind: A1
- Application number: 12/636,901
- Filed: 2009-12-14
- Published: 2010-07-01
- Earliest claimed: 2008-12-26
- Assignees: Hynix Semiconductor Inc.
- Inventors: Hae-Rang CHOI; Yong-Ju KIM; Sung-Woo HAN; Hee-Woong SONG; Ic-Su OH; Hyung-Soo KIM; Tae-Jin HWANG; Ji-Wang LEE; Jae-Min JANG; Chang-Kun PARK
- Web page: https://patentgrep.com/patent/US20100164568A1

## CPC

- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A variable delay circuit includes at least a fixed delay unit, a first selection unit, and variable delay unit. The fixed delay unit receives an input signal and a first delay selection signal indicative of a first delay, and outputs a first delayed signal that is substantially the input signal delayed by the first delay. The first selection unit receives the input signal, the first delayed signal, and a second delay selection signal, and outputs either the input signal or the first delayed signal based on the second delay selection signal to the variable delay unit. The variable delay unit also receives a third delay selection signal indicative of a third delay, and outputs a output signal that is substantially the output signal of the selection unit delayed by a third delay. The first delay is 0 or X multiples of M delay units. The third delay is a delay selected from 0 to N delay units.

## Claims

### Claim 1

A variable delay circuit comprising:
a fixed delay unit receiving an input signal and at least one first delay selection signal indicative of a first delay, the fixed delay unit outputting a first delayed signal that is substantially the input signal delayed by the first delay;
a first selection unit receiving the input signal, the first delayed signal, and at least one second delay selection signal, the first selection unit outputting either the input signal or the first delayed signal based on the at least one second delay selection signal; and
a variable delay unit receiving the output signal of the first selection unit and at least one third delay selection signal indicative of a third delay, the variable delay unit outputting a delayed output signal that is substantially the output signal of the selection unit delayed by a third delay.

### Claim 2 (depends on 1)

The variable delay circuit of claim 1, wherein the first delay is 0 or a fixed delay of X multiples of M unit delays, and wherein the third delay is a delay selected from 0 to N unit delays, where X, M, or N is a positive integer.

### Claim 3 (depends on 2)

The variable delay circuit of claim 2, wherein one unit delay substantially equals one predetermined cycle of a clock signal utilized in the variable delay circuit.

### Claim 4 (depends on 2)

The variable delay circuit of claim 2, wherein the fixed delay unit comprises:
X number of fixed delay parts, each delaying an inputted signal by M unit delays;
X−1 number of selection parts, each receiving one of X−1 number of first selection signals,
wherein the X number of fixed delay parts and the X−1 number of selection parts are connected in series in an alternating manner such that one selection part is connected between two fixed delay parts;
wherein the input signal is applied to the first fixed delay part of the series and to each of the selection parts in the series;
wherein each selection part receives the delayed output of the previous connected fixed delay part and outputs either the received delayed signal or the input signal to the next fixed delay part connected in series; and
wherein the last fixed delay part connected in series outputs the delayed signal to the first selection unit.

### Claim 5 (depends on 4)

The variable delay circuit of claim 4, wherein the selection part outputs the received delayed signal when the received one of X−1 number of the first selection signal is at a predetermined level and outputs the input signal when the received one of X−1 number of the first selection signal is not at a predetermined level.

### Claim 6 (depends on 5)

The variable delay circuit of claim 5, wherein the fixed delay part comprises M number of delay elements including flip flops, wherein each delay elements is configured to provide 1 unit delay.

### Claim 7 (depends on 4)

The variable delay circuit of claim 4, wherein the first selection unit outputs the first delayed signal when the second delay selection signal is at a predetermined level and outputs the input signal when the second delay selection signal is not at a predetermined level.

### Claim 8 (depends on 7)

The variable delay circuit of claim 7, wherein the variable delay unit comprises:
N number of delay elements connected in series, each delay element being configured to provide 1 unit delay; and
a variable selection part receiving the output of the first selection unit, the outputs of the N number of delay elements, and the third delay selection signal,
wherein the variable selection part is configured to output any one of the received signals as the output delay signal based on the third delay selection signal.

### Claim 9 (depends on 8)

The variable delay circuit of claim 8, wherein one unit delay substantially equals one predetermined cycle of a clock signal utilized in the variable delay circuit.

### Claim 10 (depends on 5)

The variable delay circuit of claim 5 further comprising:
a clock divider receiving a clock signal having a frequency of F and outputting a plurality of clock signals of different frequencies,
wherein a clock signal having a frequency equivalent to F/M is provided to the fixed delay unit, and
wherein the plurality of clock signals having frequencies of F/Y, Y being M to 1, are provided to a variable delay part.

### Claim 11 (depends on 10)

The variable delay circuit of claim 10, wherein each of the fixed delay part comprises one delay element including a flip flop such that each delay element receiving the clock signal having a frequency equivalent to F/M is configured to provide a delay of M unit delays.

### Claim 12 (depends on 11)

The variable delay circuit of claim 11, wherein the first selection unit outputs the first delayed signal when the second delay selection signal is at a predetermined level and outputs the input signal when the second delay selection signal is not at a predetermined level.

### Claim 13 (depends on 12)

The variable delay circuit of claim 12, wherein the variable delay unit comprises:
a clock selection part receiving the plurality of clock signals having frequencies of F/Y, Y being M to 1 and one or more of the third delay selection signals, and outputting one of the plurality of clock signals to a variable delay part; and
the variable delay part comprising one delay element including a flip flop such that the variable delay part receiving the clock signal having a frequency equivalent to F/Y, Y being M to 1, is configured to provide a output signal having a delay of 1 to M unit delays.

### Claim 14 (depends on 13)

The variable delay circuit of claim 13, the variable delay unit further comprising:
a second selection unit receiving the output signal of the variable delay part, the input signal, and at least one fourth delay selection signal, the second selection unit outputting either the input signal or the output signal of the variable delay part based on the at least one fourth delay selection signal.

### Claim 15 (depends on 14)

The variable delay circuit of claim 14, wherein the second selection unit outputs the output signal of the variable delay part when the fourth delay selection signal is at a predetermined level and outputs the input signal when the fourth delay selection signal is not at a predetermined level.

### Claim 16 (depends on 15)

The variable delay circuit of claim 15, wherein one unit delay substantially equals one predetermined cycle of a clock signal utilized in the variable delay circuit.

### Claim 17 (depends on 5)

The variable delay circuit of claim 5, wherein the fixed delay part comprises:
a counting controller determining when to begin a counting operation and outputting a toggling signal;
a counting part counting the toggling signal and outputting a first counting code, wherein an initial value of the first counting code is a fixed value;
an output signal generating part outputting a signal when the first counting code reaches a predetermined value.

### Claim 18 (depends on 17)

The variable delay circuit of claim 17, wherein the first selection unit outputs the first delayed signal when the second delay selection signal is at a predetermined level and outputs the input signal when the second delay selection signal is not at a predetermined level.

### Claim 19 (depends on 18)

The variable delay circuit of claim 18, wherein the variable delay unit comprises:
a counting controller determining when to begin a counting operation and outputting a toggling signal;
a counting part receiving the third selection delay signal and counting the toggling signal and outputting a second counting code, wherein an initial value of the second counting code is determined based on the third delay selection signal;
an output signal generating part outputting a signal when the second counting code reaches the predetermined value.

### Claim 20 (depends on 19)

The variable delay circuit of claim 19 further comprising:
a second selection unit receiving the output signal of the variable delay unit, the input signal, and at least one fourth delay selection signal, the second selection unit outputting either the input signal or the output signal of the variable delay unit based on the at least one fourth delay selection signal.

### Claim 21 (depends on 20)

The variable delay circuit of claim 20, wherein the second selection unit outputs the output signal of the variable delay unit when the fourth delay selection signal is at a predetermined level and outputs the input signal when the fourth delay selection signal is not at a predetermined level.

### Claim 22 (depends on 19)

The variable delay circuit of claim 19, wherein one unit delay substantially equals one predetermined cycle of a clock signal utilized in the variable delay circuit.

### Claim 23 (depends on 8)

The variable delay circuit of claim 8, wherein the third delay selection signal comprises N+1 number of signals.

### Claim 24 (depends on 10)

The variable delay circuit of claim 10, wherein the number of clock signals is M.

### Claim 25 (depends on 17)

The variable delay circuit of claim 17, wherein the counting part performs M number of counting operations.