# US 2010/0164559 A1 · Power-on circuit

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- Number: US 2010/0164559 A1
- Document ID: US20100164559A1
- Status: Published application
- Kind: A1
- Application number: 12/641,097
- Filed: 2009-12-17
- Published: 2010-07-01
- Earliest claimed: 2008-12-30
- Inventors: Sung-Jin Park
- Web page: https://patentgrep.com/patent/US20100164559A1

## CPC

- H03K 17/223: {in field-effect transistor switches}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

The power-on circuit includes a first I/O voltage detector configured to detect whether or not an I/O voltage is applied and output an I/O voltage detection signal based on the detected result, a second I/O voltage detector configured to detect when the applied I/O voltage becomes a reference level value and output a cut signal based on the detected result, a core voltage detector configured to detect whether or not a core voltage is applied and output a core voltage detection signal based on the detected result, and a power-on signal generator configured to generate a power-on signal based on the I/O voltage detection signal, the cut signal and the core voltage detection signal and forcibly generate the power-on signal if the I/O voltage is stabilized later than the core voltage.

## Claims

### Claim 1

An apparatus comprising:
a first Input/Output (I/O) voltage detector configured to detect whether or not an I/O voltage is applied and output an I/O voltage detection signal based on the detected result;
a second I/O voltage detector configured to detect when the applied I/O voltage becomes a reference level value and output a cut signal based on the detected result;
a core voltage detector configured to detect whether or not a core voltage is applied and output a core voltage detection signal based on the detected result; and
a power-on signal generator configured to generate a power-on signal based on the I/O voltage detection signal, the cut signal and the core voltage detection signal and forcibly generate the power-on signal if the I/O voltage is stabilized later than the core voltage.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the reference level value is a normal state value of the I/O voltage.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the reference level value is in a range between 80 to 99% of the normal state value.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the power-on signal generator comprises:
a first conductive type first transistor including a source to which the I/O voltage is applied, a drain, and a first gate to which the I/O voltage detection signal is applied;
a second conductive type first transistor including a drain connected to the drain of the first conductive type first transistor, a source and a second gate to which the cut signal is input;
a second conductive type second transistor including a drain connected to the source of the second conductive type first transistor, a source connected to a ground voltage, and a third gate;
a power signal controller configured to control the voltage applied to the third gate of the second conductive type second transistor based on the cut signal;
a latch connected to a connection node between the drain of the first conductive type first transistor and the drain of the second conductive type first transistor; and
a logic operation unit configured to logically operate a signal stored in the latch and the I/O voltage detection signal and output the power-on signal based on the logically operated result.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the power signal controller comprises:
a second conductive type first load transistor including a source, a drain to which the cut signal is applied, and a fourth gate connected to the source; and
a second conductive type second load transistor including a drain connected to the source of the second conductive type first load transistor and the gate of the second conductive type second transistor, a source connected to the ground voltage, and a fifth gate connected to the source.

### Claim 6 (depends on 4)

The apparatus of claim 4, wherein the logic operation unit comprises:
a NAND gate configured to logically operate a signal stored in the latch and the I/O voltage detection signal and to output the logically operated signal; and
an inverter configured to invert the result logically operated by the NAND gate and to output the inverted result.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the apparatus comprises a power-on circuit.

### Claim 8

An apparatus comprising:
a first voltage detector configured to detect whether or not an I/O voltage is applied and output an I/O voltage detection signal based on the detected result;
a second voltage detector configured to detect when the applied I/O voltage becomes a reference level value and output a cut signal based on the detected result;
a third voltage detector configured to detect whether or not a core voltage is applied and output a core voltage detection signal based on the detected result; and
a power signal generator configured to generate a power-on signal which controls an I/O circuit of a semiconductor chip and forcibly generates the power-on signal if the I/O voltage is stabilized later than the core voltage.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the apparatus comprises a power-on circuit.

### Claim 10 (depends on 8)

The apparatus of claim 8, wherein the power-on signal is based on the I/O voltage detection signal, the cut signal and the core voltage detection signal.

### Claim 11 (depends on 8)

The apparatus of claim 8, wherein if the I/O voltage is applied and is less than a first reference voltage, the first voltage detector outputs an I/O voltage detection signal having a first voltage level.

### Claim 12 (depends on 9)

The apparatus of claim 9, wherein if the I/O voltage is applied and is greater than a first reference voltage, the first voltage detector outputs I/O voltage detection signal having a second voltage level.

### Claim 13 (depends on 12)

The apparatus of claim 12, wherein the first voltage level is less than the second voltage level.

### Claim 14 (depends on 13)

The apparatus of claim 13, wherein the first voltage level and the second voltage level are determined according to chip driving characteristics.

### Claim 15 (depends on 8)

The apparatus of claim 8, wherein if the I/O voltage is applied and is greater than a first reference voltage, the first voltage detector outputs I/O voltage detection signal having a second level.

### Claim 16 (depends on 8)

The apparatus of claim 8, wherein if the core voltage is applied and is less than a second reference voltage, the third voltage detector outputs the core voltage detection signal having a first voltage level.

### Claim 17 (depends on 16)

The apparatus of claim 16, wherein if the core voltage is applied and is greater than the second reference voltage, the third voltage detector outputs the core voltage detection signal having a second voltage level.

### Claim 18 (depends on 8)

The apparatus of claim 8, wherein the power signal generator comprises:
a first transistor having a first conductive type including a source to which the I/O voltage is applied, a drain, and a first gate to which the I/O voltage detection signal is applied;
a second transistor having a second conductive type including a drain connected to the drain of the first transistor, a source and a second gate to which the cut signal is input;
a third transistor having a second conductive type including a drain connected to the source of the second transistor, a source connected to a ground voltage, and a third gate;
a power signal controller configured to control the voltage applied to the third gate of the third transistor based on the cut signal;
a latch connected to a connection node between the drain of the first transistor and the drain of the second transistor; and
a logic operation unit configured to logically operate a signal stored in the latch and the I/O voltage detection signal and output the power-on signal based on the logically operated result.

### Claim 19 (depends on 18)

The apparatus of claim 18, wherein the power signal controller comprises:
a first load transistor having a second conductive type including a source, a drain to which the cut signal is applied, and a fourth gate connected to the source; and
a second load transistor having a second conductive type including a drain connected to the source of the first load transistor and the third gate of the third transistor, a source connected to the ground voltage, and a fifth gate connected to the source.

### Claim 20 (depends on 18)

The apparatus of claim 18, wherein the logic operation unit comprises:
a NAND gate configured to logically operate a signal stored in the latch and the I/O voltage detection signal and to output the logically operated signal; and
an inverter configured to invert the result logically operated by the NAND gate and to output the inverted result.