# US 2010/0164541 A1 · Termination control circuit and method for global input/output line

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- Number: US 2010/0164541 A1
- Document ID: US20100164541A1
- Status: Published application
- Kind: A1
- Application number: 12/493,266
- Filed: 2009-06-29
- Published: 2010-07-01
- Earliest claimed: 2008-12-30
- Assignees: Hynix Semiconductor Inc.
- Inventors: Ki Up Kim
- Web page: https://patentgrep.com/patent/US20100164541A1

## CPC

- H03K 19/0005: {Modifications of input or output impedance}
- G11C 7/02: with means for avoiding parasitic signals
- G11C 7/1048: {Data bus control circuits, e.g. precharging, presetting, equalising}
- G11C 7/1051: {Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits}
- G11C 7/1069: {I/O lines read out arrangements}
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A termination control circuit for a global input/output line includes a speed determination unit configured to output a termination enable signal which is activated in response to a frequency of an external clock signal and CAS latency information; and a pulse generation unit configured to output a driving signal for driving a termination circuit for the global input/output line in response to a termination control signal and the termination enable signal.

## Claims

### Claim 1

A termination control circuit for a global input/output line, comprising:
a speed determination unit configured to output a termination enable signal which is activated in response to a frequency of an external clock signal and CAS latency information; and
a pulse generation unit configured to output a driving signal for driving a termination circuit for the global input/output line in response to a termination control signal and the termination enable signal.

### Claim 2 (depends on 1)

The termination control circuit of claim 1, wherein the speed determination unit includes:
a frequency detection portion configured to output a frequency detection signal of at least 1 bit by detecting the frequency of the external clock signal; and
a comparison portion configured to output the termination enable signal by receiving the frequency detection signal and CAS latency information of at least 1 bit.

### Claim 3 (depends on 2)

The termination control circuit of claim 2, wherein the comparison portion enables the termination enable signal when a combination of the frequency of the external clock signal and the CAS latency information satisfies a certain combination.

### Claim 4 (depends on 2)

The termination control circuit of claim 2, wherein the comparison portion includes:
a plurality of first logical elements each configured to receive a bit of the frequency detection signal and a bit of the CAS latency information;
a plurality of inverters configured to be connected to output terminals of the plurality of first logical elements;
a second logical element configured to receive signals outputted from the plurality of inverters; and
an inverter configured to output the termination enable signal by inverting an output signal of the second logical element.

### Claim 5 (depends on 2)

The termination control circuit of claim 2, wherein the pulse generation unit includes a third logical element configured to output the driving signal by receiving the termination enable signal and an inversion signal of the termination control signal.

### Claim 6

A termination control method for a global input/output line, comprising:
determining whether or not a frequency of an external clock signal and CAS latency information satisfy a certain combination in response to receipt of the external clock signal and the CAS latency information; and
outputting a driving signal for driving a termination circuit for a global input/output line when the frequency of the external clock signal and the CAS latency information satisfy the certain combination.

### Claim 7 (depends on 6)

The termination control method of claim 6, wherein determining whether or not the frequency of the external clock signal and the CAS latency information satisfy the certain combination includes:
detecting the frequency of the external clock signal; and
comparing CAS latency information with the frequency detection signal.