# US 2010/0164533 A1 · Method and apparatus for evaluating the effects of stress on an rf oscillator > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2010/0164533 A1 - Document ID: US20100164533A1 - Status: Published application - Kind: A1 - Application number: 12/352,795 - Filed: 2009-01-13 - Published: 2010-07-01 - Earliest claimed: 2008-12-31 - Assignees: Texas Instruments Incorporated - Inventors: Andrew Marshall; Srikanth Krishnan - Web page: https://patentgrep.com/patent/US20100164533A1 ## CPC - G01R 31/2617: {for measuring switching properties thereof} - G01R 31/2824: {testing of oscillators or resonators} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract Apparatus and methods are disclosed for evaluating degradation of a transistor in a cross coupled pair of an RF oscillator independently. A MOS device can be coupled between a separated center-tap inductor. By appropriately sizing the MOS device and turning the MOS device on during operation of RF oscillator, a good contact can again be made that allows the oscillator to operate at design performance. By turning the MOS device off, the supplies can be separates such that I-V characteristics of both transistors of the cross-coupled pair may be obtained. ## Claims ### Claim 1 A method to evaluate optimum power transistor switching characteristics for determining reliability limitations in an RF oscillator circuit, the method comprising: providing a cross-coupled transistor circuit comprising a first transistor and a second transistor, and coupled to a resonant tank, wherein the resonant tank comprises a center-tap inductor and at least one capacitor; splitting the center-tap inductor into a plurality of inductors comprising a first inductor with a first output and a second inductor with a second output; coupling a third transistor to the first output and to the second output located between the first inductor and the second inductor; turning the third transistor off; and testing at least one DC characteristic of the first transistor and testing at least one DC characteristic of the second transistor. ### Claim 2 (depends on 1) The method of claim 1, further comprising turning the third transistor on for operation as an RF oscillator circuit. ### Claim 3 (depends on 1) The method of claim 1, wherein testing the at least one DC characteristic comprises determining a degradation of the first transistor and a degradation of the second transistor. ### Claim 4 (depends on 1) The method of claim 1, wherein testing at least one DC characteristic of the first transistor and of the second transistor comprises testing at least one DC characteristic of the first transistor while the second transistor is off, and testing at least one DC characteristic of the second transistor while the first transistor is off, and wherein the DC characteristic comprise a leakage of the first transistor and the second transistor respectively. ### Claim 5 (depends on 1) The method of claim 1, wherein testing at least one DC characteristic is performed independently of the second transistor when the first transistor is being tested, and performed independently of the first transistor when the second transistor is being tested, and wherein testing does not introduce any additional capacitances and inductances. ### Claim 6 (depends on 1) The method of claim 1, wherein the third transistor comprises a MOSFET device. ### Claim 7 (depends on 1) The method of claim 1, further comprising determining a product defined mismatch between the first transistor and the second transistor before any stress voltage application has been applied. ### Claim 8 (depends on 1) The method claim 1, wherein the DC characteristic comprises a gate/drain stress characteristic determining reliability variation as a function of gate/drain voltage. ### Claim 9 A circuit to allow analysis of stress characteristics in RF circuitry for determining reliability variation as a function of voltage, comprising: a first transistor and a second transistor coupled in a cross-coupled configuration, wherein a first gate terminal of the first transistor is coupled to a second drain terminal of the second transistor, and a second gate terminal of the second transistor is coupled to a first drain terminal of the first transistor; a resonant tank comprising a center-tap inductor comprising a plurality of inductors comprising a first inductor comprising a first output and a second inductor comprising a second output, at least one capacitor, and a third transistor; wherein the third transistor is coupled to the first inductor and to the second inductor. ### Claim 10 (depends on 9) The circuit of claim 9, wherein the third transistor is a MOSFET device ### Claim 11 (depends on 9) The circuit of claim 9, wherein the capacitor is coupled in a parallel configuration to the center-tap inductor and the third transistor. ### Claim 12 (depends on 9) The circuit of claim 9, wherein the resonant tank is coupled to the first drain terminal of the first transistor and the second drain terminal of the second transistor. ### Claim 13 (depends on 9) The circuit of claim 9, further comprising a measurement device coupled to the first output of the first inductor or the second output of the second inductor, and configured to measure a degradation characteristic of the first transistor independent of the second transistor, and to measure a degradation of the second transistor independent of the first transistor. ### Claim 14 (depends on 13) The circuit of claim 13, wherein the degradation characteristic measured comprises a gate/drain stress characteristic as a function of gate/drain voltage for determining reliability variation. ### Claim 15 A circuit to allow analysis of stress characteristics in RF circuitry for determining reliability variation as a function of voltage, comprising: a first transistor and a second transistor coupled in a cross-coupled configuration, wherein a first gate terminal of the first transistor is coupled to a second drain terminal of the second transistor, and a second gate terminal of the second transistor is coupled to a first drain terminal of the first transistor; a center-tap inductor comprising a plurality of inductors comprising a first inductor comprising a first output and a second inductor comprising a second output; a capacitor; and a third transistor; wherein the third transistor is coupled to the first inductor and to the second inductor. ### Claim 16 (depends on 15) The circuit of claim 15, wherein the third transistor is a pMOS device. ### Claim 17 (depends on 15) The circuit of claim 15, wherein the capacitor is coupled in a parallel configuration to the center-tap inductor and the third transistor. ### Claim 18 (depends on 17) The circuit of claim 17, wherein the parallel configuration is coupled to the first drain terminal of the first transistor and the second drain terminal of the second transistor. ### Claim 19 (depends on 15) The circuit of claim 15, further comprising a measurement device coupled to the first output of the first inductor or the second output of the second inductor, and configured to measure a degradation characteristic of the first transistor independent of the second transistor, and to measure a degradation of the second transistor independent of the first transistor. ### Claim 20 (depends on 19) The circuit of claim 19, wherein the degradation characteristic measured comprises a gate/drain stress characteristic as a function of gate/drain voltage for determining reliability variation.