# US 2010/0164477 A1 · High speed voltage regulator with integrated loseless current sensing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2010/0164477 A1 - Document ID: US20100164477A1 - Status: Published application - Kind: A1 - Application number: 12/347,711 - Filed: 2008-12-31 - Published: 2010-07-01 - Earliest claimed: 2008-12-31 - Inventors: Malay Trivedi; Jiang William; Brent D. Thomas; James T. Doyle; Rose Wang - Web page: https://patentgrep.com/patent/US20100164477A1 ## CPC - G06F 1/26: Power supply means, e.g. regulation thereof (for memories G11C) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract In general, in one aspect, the disclosure describes a high-speed multi-phase voltage regulator (VR) capable of sensing load current. For each phase leg, the VR includes a current mirror to mirror current in switching elements, a current sense to sense high side current in the current mirror, and a I-V converter to convert the sensed high side current to a voltage. The high side sensed current for each phase leg is averaged and the duty cycle for the VR is extracted. The average high side sensed current and the duty cycle are converted to digital by an A-D converter. Digital circuitry corrects the sensed current by adjusting for the gain and offset voltage of the VR. The adjusted sensed value is divided by the duty cycle to convert to load current and the average load current is multiplied by the number of phases operating to determine overall load current. ## Claims ### Claim 1 An apparatus comprising an analog domain to perform current sensing for each phase of a voltage regulator (VR) and average the sensed currents from each phase to generate an average sensed current of the VR; and a digital domain to perform post-processing on the average sensed current to calculate load current. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the analog domain includes a current mirror for each phase of the VR, wherein each current mirror is to mirror current in bridge of each respective phase of the VR; a current sense for each phase of the VR, wherein each current sense is to sense high side current in the respective current mirror; and an averager to receive the high side sensed current for each phase and to generate the average sensed current of the VR. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the analog domain further includes a current to voltage (IV) converter for each phase of the VR, wherein each IV converter is to convert the associated sensed high side current to a voltage representing the sensed high side current, wherein the averager is to receive the voltage representing the high side sensed current for each phase and to generate a voltage representing the average sensed current for the VR. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the analog domain further includes a voltage gain stage for each phase of the VR. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the analog domain is further to measure duty cycle of the VR. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the digital domain is to receive the average sensed current of the VR and the duty cycle of the VR and to use these values to calculate the load current. ### Claim 7 (depends on 6) The apparatus of claim 6, wherein the digital domain is to adjust the average sensed current to adjust for errors in measurement thereof. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein the errors adjusted for include offset voltage and gain of the VR. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein the digital domain is to receive correction values for the offset voltage and the gain from the VR, wherein the correction values are determined during test of the VR. ### Claim 10 A voltage regulator (VR) comprising a plurality of phase legs commonly coupled to a regulated voltage node, wherein each phase leg is to deliver switchably controlled current from an applied voltage source to a load through the regulated voltage node, wherein each of the plurality of phase legs includes a current mirror to mirror current in switching elements; and a current sense to sense high side current in the current mirror; an averager to receive the high side sensed current for each phase leg and to generate an average sensed current for the plurality of phase legs; and a digital correction circuitry to correct errors in the average sensed current and convert the corrected sensed current to load current. ### Claim 11 (depends on 10) The VR of claim 10, wherein the digital correction circuitry is to modify the average sensed current to account for offset voltage and gain of the VR. ### Claim 12 (depends on 11) The VR of claim 11, further comprising a duty cycle extractor to extract the duty cycle of the VR, wherein the digital correction circuitry is to use the duty cycle to convert the corrected average sensed current to average load current. ### Claim 13 (depends on 12) The VR of claim 12, wherein the digital correction circuitry is to determine number of phases operating and multiply average load current by the number of phases to determine the load current. ### Claim 14 (depends on 10) The VR of claim 10, further comprising platform diagnostics to analyze load power consumption. ### Claim 15 (depends on 10) The VR of claim 10, further comprising phase balancing circuitry to balance the VR based on the sensed current for each phase. ### Claim 16 (depends on 10) The VR of claim 10, wherein the current mirrors include a plurality of transistors in series. ### Claim 17 (depends on 10) The VR of claim 10, wherein each of the plurality of phase legs further includes a current to voltage (IV) converter to convert the sensed high side current to a voltage representing the sensed high side current. ### Claim 18 (depends on 12) The VR of claim 12, further comprising an analog-to-digital converter to convert the duty cycle and average sensed current to digital.