# US 2010/0164468 A1 · Work Function Based Voltage Reference

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- Number: US 2010/0164468 A1
- Document ID: US20100164468A1
- Status: Published application
- Kind: A1
- Application number: 12/719,501
- Filed: 2010-03-08
- Published: 2010-07-01
- Earliest claimed: 2008-04-07
- Assignees: Microchip Technology Incorporated
- Inventors: Gregory Dix
- Web page: https://patentgrep.com/patent/US20100164468A1

## CPC

- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/83125: {the IGFETs characterised by having shared source or drain regions}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D 84/014: {the gate conductors having different materials or different implants}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A voltage reference is created from an operational amplifier circuit having two substantially identical P-channel metal oxide semiconductor (P-MOS) transistors with each one having a different gate dopant. The different gate dopants result in different threshold voltages for each of the two otherwise substantially identical P-MOS transistors. The difference between these two threshold voltages is then used to create the voltage reference equal to the difference. The two P-MOS transistors are configured as a differential pair in the operational amplifier circuit and the output of the operational amplifier is used as the voltage reference.

## Claims

### Claim 1

A voltage reference fabricated on an integrated circuit die, comprising:
a first P-channel metal oxide semiconductor (P-MOS) transistor having an N-type polysilicon gate, wherein the N-type polysilicon gate causes the first P-MOS transistor to have a first threshold voltage;
a second P-MOS transistor having a P-type polysilicon gate, wherein the P-type polysilicon gate causes the second P-MOS transistor to have a second threshold voltage;
the first and second P-MOS transistors are configured as a differential pair of an operational amplifier; and
the operational amplifier has an output voltage substantially equal to a difference between the first and the second threshold voltages.

### Claim 2 (depends on 1)

The voltage reference according to claim 1, wherein the first threshold voltage is about a minus 1.4 volts.

### Claim 3 (depends on 2)

The voltage reference according to claim 2, wherein the second threshold voltage is about a minus 0.3 volts.

### Claim 4 (depends on 3)

The voltage reference according to claim 3, wherein the output voltage of the operational amplifier is about 1.1 volts.

### Claim 5 (depends on 1)

The voltage reference according to claim 1, further comprising a lightly doped P-type implant in an N-type well/region of the integrated circuit die where gate channels of the first and second P-MOS transistors are located.

### Claim 6 (depends on 5)

The voltage reference according to claim 5, wherein the first threshold voltage is about a minus 1.1 volts.

### Claim 7 (depends on 6)

The voltage reference according to claim 6, wherein the second threshold voltage is about 0.0 volts.

### Claim 8 (depends on 7)

The voltage reference according to claim 7, wherein the output voltage of the operational amplifier is about 1.1 volts.

### Claim at position 9

9-14. (canceled)