# US 2010/0164115 A1 · Semiconductor chip package

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- Number: US 2010/0164115 A1
- Document ID: US20100164115A1
- Status: Published application
- Kind: A1
- Application number: 12/649,257
- Filed: 2009-12-29
- Published: 2010-07-01
- Earliest claimed: 2008-12-31
- Inventors: Jung-Hyun Yo
- Web page: https://patentgrep.com/patent/US20100164115A1

## CPC

- H10W 72/00: Interconnections or connectors in packages
- H10W 72/90: Bond pads, in general
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A device and/or method relating to semiconductor technology. A semiconductor chip package may include dual line type input/output (I/O) pads. A semiconductor chip package may include a core area. A semiconductor chip package may include input/output (I/O) pads arranged on and/or over an outside of a core area, which may signal input/output to and/or from a core area. A semiconductor chip package may have input/output (I/O) pads including dual lines.

## Claims

### Claim 1

An apparatus comprising:
a core area; and
input/output pads arranged over an outside of a core area configured to signal at least one of an input and an output to and from said core area.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein said input/output pads comprise dual lines.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein said dual lines comprise an inner line including a first group of input/output pads and an outer line including a second group of input/output pads.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein said input/output pads of said inner line and said input/output pads of said outer line are arranged to straddle over each other.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein said input/output pads of said inner line and said input/output pads of said outer line are arranged opposite to each other.

### Claim 6 (depends on 3)

The apparatus of claim 3, wherein said input/output pads of said inner line are arranged at a side of said core area, and said input/output pads of said outer line are arranged at an outside of said input/output pads of said inner line.

### Claim 7 (depends on 3)

The apparatus of claim 3, wherein said input/output pads of said inner line and said input/output pads of said outer line comprise an in-line type which is physically rectangular having a length greater than a width.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein said input/output pads of said inner line and said input/output pads of said outer line comprises a width substantially the same as a width of said in-line type input/output pads and a length shorter than a length of said in-line type input/output pads.

### Claim 9 (depends on 1)

The apparatus of claim 1, comprising a reserved space between said input/output pads and said core area.

### Claim 10 (depends on 1)

The apparatus of claim 1, comprising a semiconductor chip package.

### Claim 11

A method comprising:
forming a core area; and
forming input/output pads arranged over an outside of a core area configured to signal at least one of an input and an output to and from said core area.

### Claim 12 (depends on 11)

The method of claim 11, wherein said input/output pads comprise dual lines.

### Claim 13 (depends on 12)

The method of claim 12, wherein said dual lines comprise an inner line including a first group of input/output pads and an outer line including a second group of input/output pads.

### Claim 14 (depends on 13)

The method of claim 13, wherein said input/output pads of said inner line and said input/output pads of said outer line are arranged to straddle over each other.

### Claim 15 (depends on 14)

The method of claim 14, wherein said input/output pads of said inner line and said input/output pads of said outer line are arranged opposite to each other.

### Claim 16 (depends on 13)

The method of claim 13, wherein said input/output pads of said inner line are arranged at a side of said core area, and said input/output pads of said outer line are arranged at an outside of said input/output pads of said inner line.

### Claim 17 (depends on 13)

The method of claim 13, wherein said input/output pads of said inner line and said input/output pads of said outer line comprise an in-line type which is physically rectangular having a length greater than a width.

### Claim 18 (depends on 17)

The method of claim 17, wherein said input/output pads of said inner line and said input/output pads of said outer line comprises a width substantially the same as a width of said in-line type input/output pads and a length shorter than a length of said in-line type input/output pads.

### Claim 19 (depends on 11)

The method of claim 11, comprising a reserved space between said input/output pads and said core area.

### Claim 20 (depends on 11)

The method of claim 11, comprising a semiconductor chip package.