# US 2010/0164099 A1 · Semiconductor integrated circuit device

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- Number: US 2010/0164099 A1
- Document ID: US20100164099A1
- Status: Published application
- Kind: A1
- Application number: 12/659,462
- Filed: 2010-03-09
- Published: 2010-07-01
- Earliest claimed: 2007-10-09
- Assignees: Fujitsu Limited
- Inventors: Yasuhide Sosogi
- Web page: https://patentgrep.com/patent/US20100164099A1

## CPC

- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- H10B 99/22: {including field-effect components}
- H10W 20/427: {Power or ground buses}
- G11C 2029/1206: {Location of test circuitry on chip or wafer}
- H10D 84/907: {CMOS gate arrays}
- H10D 89/00: Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor integrated circuit device includes plural circuit units each having plural logic circuits; and plural power terminals supplying power source from outside to the semiconductor integrated circuit device, in which the plural circuit units each having plural logic circuits have common packaging design with each other, and lengths in a vertical direction and a lateral direction of the circuit units each having plural logic circuits are equal to an even multiple of a distance between the power terminals adjacent to each other.

## Claims

### Claim 1

A semiconductor integrated circuit device comprising:
plural units each having plural logic circuits; and
plural power terminals configured to supply a power source from outside to the semiconductor integrated circuit device, wherein
the plural units each having plural logic circuits have common packaging design with each other, and
lengths in a vertical direction and a lateral direction of the units each having plural logic circuits are equal to an even multiple of a distance between the power terminals adjacent to each other.

### Claim 2 (depends on 1)

The semiconductor integrated circuit device according to claim 1, wherein
each of the plural units each having plural logic circuits includes respective power source patterns connected to the power terminals, and
an even number of the power terminals belong to each of the plural units each having plural logic circuits.

### Claim 3 (depends on 1)

The semiconductor integrated circuit device according to claim 1, wherein
the plural units each having plural logic circuits are cache memories.

### Claim 4 (depends on 3)

The semiconductor integrated circuit device according to claim 3, wherein
the cache memory includes at least one of a logic circuit having a repeated pattern, a test circuit, and a standard cell.

### Claim 5

A semiconductor device comprising:
plural bumps arranged at regular intervals; and
a cache memory, wherein
lengths in a vertical direction and a lateral direction of the cache memory are equal to an even multiple of a distance between the bumps adjacent to each other.

### Claim 6

A method of designing a semiconductor device having plural bumps arranged at regular intervals and a cache memory, the method comprising:
designing in a manner such that lengths in a vertical direction and a lateral direction of the cache memory are equal to an even multiple of a distance between the bumps adjacent to each other.