# US 2010/0164097 A1 · Semiconductor Device and Method of Confining Conductive Bump Material During Reflow with Solder Mask Patch > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2010/0164097 A1 - Document ID: US20100164097A1 - Status: Published application - Kind: A1 - Application number: 12/633,531 - Filed: 2009-12-08 - Published: 2010-07-01 - Earliest claimed: 2008-12-31 - Assignees: STATS ChipPAC, Ltd. - Inventors: Rajendra D. Pendse - Web page: https://patentgrep.com/patent/US20100164097A1 ## CPC - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H05K 3/3436: {having an array of bottom contacts, e.g. pad grid array or ball grid array components} - H05K 3/3452: Solder masks - H10W 70/65: Shapes or dispositions of interconnections - H10W 72/012: {of bump connectors, dummy bumps or thermal bumps} - H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H05K 2201/09909: Special local insulating pattern, e.g. as dam around component - H05K 2201/10674: Flip chip - H10W 70/655: Fan-out layouts - H10W 70/682: {comprising holes having chips therein} - H10W 72/019: {of bond pads} - H10W 72/07251: {characterised by changes in properties of the bump connectors during connecting} - H10W 72/07554: {changes in dispositions} - H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core} - H10W 72/234: {Cross-sectional shape, i.e. in side view} - H10W 72/242: {relative to the surface, e.g. recessed, protruding} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/30: Die-attach connectors - H10W 72/856: {Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15)} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 72/90: Bond pads, in general - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - Y02P 70/50: Manufacturing or production processes characterised by the final manufactured product - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS ## Abstract A semiconductor device has a semiconductor die with die bump pads and substrate with trace lines having integrated bump pads. A solder mask patch is formed interstitially between the die bump pads or integrated bump pads. The solder mask patch contains non-wettable material. Conductive bump material is deposited over the integrated bump pads or die bump pads. The semiconductor die is mounted over the substrate so that the conductive bump material is disposed between the die bump pads and integrated bump pads. The bump material is reflowed without a solder mask around the integrated bump pads to form an interconnect between the semiconductor die and substrate. The solder mask patch confines the conductive bump material within a footprint of the die bump pads or integrated bump pads during reflow. The interconnect can have a non-fusible base and fusible cap. ## Claims ### Claim 1 A method of making a semiconductor device, comprising: providing a semiconductor die having die bump pads; providing a substrate having trace lines with integrated bump pads; forming a solder mask patch interstitially between the die bump pads or integrated bump pads; depositing conductive bump material on the integrated bump pads or die bump pads; mounting the semiconductor die over the substrate so that the conductive bump material is disposed between the die bump pads and integrated bump pads; and reflowing the conductive bump material without a solder mask around the integrated bump pads to form an interconnect between the semiconductor die and substrate, wherein the solder mask patch confines the conductive bump material within a footprint of the die bump pads or integrated bump pads during reflow. ### Claim 2 (depends on 1) The method of claim 1, wherein the solder mask patch includes non-wettable material. ### Claim 3 (depends on 1) The method of claim 1, further including immersing the conductive bump material in a flux solution to increase wettability. ### Claim 4 (depends on 1) The method of claim 1, wherein the interconnect includes a non-fusible base and fusible cap. ### Claim 5 (depends on 1) The method of claim 1, wherein a volume of conductive bump material deposited between the die bump pads and integrated bump pads is selected so that a surface tension maintains confinement of the conductive bump material substantially within the footprint of the die bump pads and integrated bump pads during reflow. ### Claim 6 (depends on 1) The method of claim 1, wherein a height of the interconnect is equal to or less than a diameter of the interconnect. ### Claim 7 (depends on 1) The method of claim 1, wherein an escape pitch of the trace line is given by (1.1 D+W)/2, wherein D is a diameter of the interconnect and W is the width of the trace line. ### Claim 8 A method of making a semiconductor device, comprising: providing a first semiconductor structure having first bump pads; providing a second semiconductor structure having second bump pads; forming a solder mask patch between the first bump pads or second bump pads; depositing conductive bump material between the first and second bump pads; mounting the first semiconductor structure over the second semiconductor structure so that the conductive bump material is disposed between the first bump pads and second bump pads; and reflowing the conductive bump material without a solder mask around the first and second bump pads to form an interconnect, wherein the solder mask patch confines the conductive bump material within a footprint of the first bump pads or second bump pads during reflow. ### Claim 9 (depends on 8) The method of claim 8, wherein the solder mask patch includes non-wettable material. ### Claim 10 (depends on 8) The method of claim 8, further including immersing the conductive bump material in a flux solution to increase wettability. ### Claim 11 (depends on 8) The method of claim 8, wherein the interconnect includes a non-fusible base and fusible cap. ### Claim 12 (depends on 8) The method of claim 8, wherein the volume of conductive bump material deposited between the first and second bump pads is selected so that a surface tension maintains confinement of the conductive bump material substantially within the first and second bump pads during reflow. ### Claim 13 (depends on 8) The method of claim 8, wherein a height of the interconnect is equal to or less than a diameter of the interconnect. ### Claim 14 A method of making a semiconductor device, comprising: providing a substrate having trace lines with integrated bump pads; forming a solder mask patch between the integrated bump pads; depositing conductive bump material on the integrated bump pads; and reflowing the conductive bump material without a solder mask around the integrated bump pads to form an interconnect, wherein the solder mask patch confines the conductive bump material within a footprint of the integrated bump pads during reflow. ### Claim 15 (depends on 14) The method of claim 14, wherein the solder mask patch includes non-wettable material. ### Claim 16 (depends on 14) The method of claim 14, further including immersing the conductive bump material in a flux solution to increase wettability. ### Claim 17 (depends on 14) The method of claim 14, wherein reflowing the conductive bump material forms an interconnect. ### Claim 18 (depends on 17) The method of claim 17, wherein the interconnect includes a non-fusible base and fusible cap. ### Claim 19 (depends on 14) The method of claim 14, wherein a volume of conductive bump material deposited over the integrated bump pads is selected so that a surface tension maintains confinement of the conductive bump material substantially within the footprint of the integrated bump pads during reflow. ### Claim 20 (depends on 14) The method of claim 14, wherein a height of the interconnect is equal to or less than a diameter of the interconnect. ### Claim 21 A semiconductor device, comprising: a semiconductor die having first bump pads; a substrate having second bump pads; a solder mask patch formed between the first bump pads or second bump pads; and an interconnect formed between the first and second bump pads by reflowing conductive bump material without a solder mask around the second bump pads, wherein the solder mask patch confines the conductive bump material within the first bump pads and second bump pads. ### Claim 22 (depends on 21) The semiconductor device of claim 21, wherein the solder mask patch includes non-wettable material. ### Claim 23 (depends on 21) The semiconductor device of claim 21, wherein the conductive bump material is immersed in a flux solution to increase wettability. ### Claim 24 (depends on 21) The semiconductor device of claim 21, wherein the interconnect includes a non-fusible base and fusible cap. ### Claim 25 (depends on 21) The semiconductor device of claim 21, wherein the volume of conductive bump material deposited between the first and second bump pads is selected so that a surface tension maintains confinement of the conductive bump material substantially within the first bump pads and second bump pads.