# US 2010/0164089 A1 · Non-Conductive Planarization of Substrate Surface for Mold Cap > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2010/0164089 A1 - Document ID: US20100164089A1 - Status: Published application - Kind: A1 - Application number: 12/278,653 - Filed: 2007-02-14 - Published: 2010-07-01 - Earliest claimed: 2006-02-15 - Assignees: NXP B.V. - Inventors: Gene Felten - Web page: https://patentgrep.com/patent/US20100164089A1 ## CPC - H10W 74/016: {using moulds} - H05K 3/3452: Solder masks - H10W 74/114: {by a substrate and the encapsulations} - H05K 3/284: {for encapsulating mounted components (H05K1/185 takes precedence)} - H05K 2201/09781: Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ## Abstract Consistent with an example embodiment, there is a method for fabricating a semiconductor package having a substrate. The method comprises defining an encapsulation boundary on a surface of the substrate; the encapsulation boundary is divided into a molding region and a non-molding region. Over the substrate, a plurality of conductive traces is provided. Each conductive trace has an inner connection located in the molding region and an outer connection located in the non-molding region. A plurality of non-conducting dummy traces across the encapsulation boundary is provided. The plurality of non-conductive dummy traces are interposed among the conductive traces and are spaced apart at an interval less than a predetermined minimum air-vein forming distance (Dmln). A solder mask over the substrate covers the conductive traces and the non-conductive dummy traces. The molding region of the substrate is encapsulated with a molding compound. ## Claims ### Claim 1 A method for fabricating a semiconductor package having a substrate, the method comprising: defining an encapsulation boundary on a surface of the substrate, the encapsulation boundary divided into a molding region and a non-molding region; providing a plurality of conductive traces over the substrate, each conductive trace having an inner connection located in the molding region and an outer connection located in the non-molding region; providing a plurality of non-conducting dummy traces across the encapsulation boundary, the plurality of dummy traces interposed among the conductive traces that are spaced apart at an interval greater than a predetermined minimum air-vein forming distance; providing a solder mask over the substrate covering the conductive traces and the non-conductive dummy traces; and encapsulating the molding region of substrate with a molding compound. ### Claim 2 (depends on 1) The method as recited in claim 1, wherein the predetermined minimum air-vein forming distance is less than about 0.9 mm. ### Claim 3 (depends on 1) The method as recited in claim 1, wherein the predetermined minimum air-vein form distance is less than about 0.5 mm. ### Claim 4 A packaging substrate having a substantially planar surface, the substrate comprising: a laminate material having a top metal layer of conductive traces of a predetermined vertical thickness, the conductive traces in a predetermined arrangement having dense regions and sparse regions of conductive traces, the sparse regions of adjacent conductive traces spaced apart a an interval greater than a predetermined minimum air-vein forming distance; a non-conducting material interspersed as dummy traces between the sparse regions of conductive traces, the dummy traces having a thickness comparable to the vertical thickness of the conductive traces, the dummy traces providing a planar surface and reducing spacing between features to an interval less than the predetermined minimum air-vein forming distance; and a solder mask applied over the substrate to cover the top metal layer and non-conducting material. ### Claim 5 (depends on 4) The IC substrate as recited in claim 4, wherein the solder mask is the same material as the non-conducting material. ### Claim 6 An integrated circuit device device comprising: an IC die mounted in a die attach area in a laminate substrate, the laminate substrate having a surface divided into a area inside an encapsulation boundary region and an area outside the encapsulation boundary region, the die attach area within the area inside the encapsulation boundary, the IC die encapsulated with a molding compound within the encapsulation boundary region; the laminate material having a top metal layer of conductive traces of a predetermined vertical thickness, the conductive traces in a predetermined arrangement having dense regions and sparse regions of conductive traces, the sparse regions of adjacent conductive traces spaced apart at an interval greater than a predetermined minimum air-vein forming distance, each conductive trace having an inner connection located inside the encapsulation boundary and an outer connection located outside the encapsulation boundary region, the inner connection of each conductive trace connecting the IC die at predefined pads; and a non-conducting material interspersed as dummy traces between the sparse regions of conductive traces across the encapsulation boundary region, the dummy traces having a thickness comparable to the vertical thickness of the conductive traces, the dummy traces providing a planar surface and reducing spacing between features to an interval less than the predetermined minimum air-vein forming distance. ### Claim 7 (depends on 6) The IC device as recited in claim 6, wherein a solder mask is deposited on the surface of the laminate substrate.