# US 2010/0164087 A1 · Semiconductor device having a stacked chip structure

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- Number: US 2010/0164087 A1
- Document ID: US20100164087A1
- Status: Published application
- Kind: A1
- Application number: 12/659,296
- Filed: 2010-03-03
- Published: 2010-07-01
- Earliest claimed: 2001-09-28
- Assignees: Rohm Co., Ltd.
- Inventors: Kazutaka Shibata
- Web page: https://patentgrep.com/patent/US20100164087A1

## CPC

- H10W 90/00: Package configurations
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 72/01: {Manufacture or treatment}
- H10W 72/07254: {changes in dispositions}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device is formed by mutually connecting a first semiconductor chip with second and third semiconductor chips arranged side by side, with the active surface of the first chip faced to those of the second and third chip. Both the second and third semiconductor chips have functional elements on their active surfaces. The first semiconductor chip has, in its active surface, a wiring for connecting the second semiconductor chip and the third semiconductor chip, and a terminal for external connection on its surface opposite to its active surface.

## Claims

### Claim 1

A device comprising:
a substrate having a substrate active surface;
a first chip connected to the substrate;
a first wiring formed in the substrate and arranged to connect the substrate to the first chip;
a second wiring formed in the first chip;
a substrate through-hole penetrating through the substrate in a thickness direction of the substrate;
a first through-hole penetrating through the first chip in a thickness direction of the first chip; and
a first bump bonding the substrate through-hole and the first through-hole, wherein
the first wiring is greater in sectional area than the second wiring.

### Claim 2 (depends on 1)

The device according to claim 1, wherein the bump is arranged beneath the first through-hole.

### Claim 3 (depends on 1)

The device according to claim 1, wherein conductors are arranged in the substrate through-hole and the first through-hole, respectively.

### Claim 4 (depends on 1)

The device according to claim 1, further comprising a second chip connected to the first chip.

### Claim 5 (depends on 4)

The device according to claim 4, further comprising a second bump arranged to connect the second chip to the first chip.

### Claim 6 (depends on 5)

The device according to claim 5, wherein the second chip has a second through-hole penetrating the second chip in a thickness direction of the second chip.

### Claim 7 (depends on 6)

The device according to claim 6, further comprising a third chip connected to the second chip.

### Claim 8 (depends on 7)

The device according to claim 7, further comprising a third bump arranged to connect the third chip to the second chip.

### Claim 9 (depends on 7)

The device according to claim 7, wherein a plurality of the second chips are stacked on one another.

### Claim 10 (depends on 7)

The device according to claim 7, wherein the third chip has no through-hole.

### Claim 11

A device comprising:
a substrate having a substrate active surface;
a first chip connected to the substrate;
a first wiring formed in the substrate and arranged to connect the substrate to the first chip;
a second wiring formed in the first chip;
a substrate through-hole penetrating through the substrate in a thickness direction of the substrate;
a first through-hole penetrating through the first chip in a thickness direction of the first chip; and
a first bump bonding the substrate through-hole and the first through-hole, wherein the first wiring is greater in width and thickness than the second wiring, or same in thickness and greater in width as compared to the second wiring, or same in width and greater in thickness as compared to the second wiring.

### Claim 12 (depends on 11)

The device according to claim 11, wherein the bump is arranged beneath the first through-hole.

### Claim 13 (depends on 11)

The device according to claim 11, wherein conductors are arranged in the substrate through-hole and the first through-hole, respectively.

### Claim 14 (depends on 11)

The device according to claim 11, further comprising a second chip connected to the first chip.

### Claim 15 (depends on 14)

The device according to claim 14, further comprising a second bump arranged to connect the second chip to the first chip.

### Claim 16 (depends on 15)

The device according to claim 15, wherein the second chip has a second through-hole penetrating the second chip in a thickness direction of the second chip.

### Claim 17 (depends on 16)

The device according to claim 16, further comprising a third chip connected to the second chip.

### Claim 18 (depends on 17)

The device according to claim 17, further comprising a third bump arranged to connect the third chip to the second chip.

### Claim 19 (depends on 17)

The device according to claim 17, wherein a plurality of the second chips are stacked on one another.

### Claim 20 (depends on 17)

The device according to claim 17, wherein the third chip has no through-hole.