# US 2010/0164083 A1 · Protective thin film coating in chip packaging

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- Number: US 2010/0164083 A1
- Document ID: US20100164083A1
- Status: Published application
- Kind: A1
- Application number: 12/345,572
- Filed: 2008-12-29
- Published: 2010-07-01
- Earliest claimed: 2008-12-29
- Assignees: Numonyx B.V.
- Inventors: Myung Jin Yim
- Web page: https://patentgrep.com/patent/US20100164083A1

## CPC

- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 74/127: {characterised by arrangements for sealing or adhesion}
- H10W 90/00: Package configurations
- H10W 72/01515: {Forming coatings}
- H10W 72/01551: {Changing the shapes of bond wires}
- H10W 72/01571: {Cleaning, e.g. oxide removal or de-smearing}
- H10W 72/07331: {Connecting techniques}
- H10W 72/075: {of bond wires}
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/5524: {comprising aluminium [Al]}
- H10W 72/5525: {comprising copper [Cu]}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A protective thin film coating for device packaging. A dielectric thin film coating is formed over die and package substrate surfaces prior to applying a molding compound. The protective thin film coating may reduce moisture penetration from the bulk molding compound or the interface between the molding compound and the die or substrate surfaces.

## Claims

### Claim 1

A method of packaging a microelectronic die, comprising:
attaching a first side of the die to a first side of a package substrate;
forming a substantially conformal dielectric thin film over a second side of the die and over the first side of the package substrate; and
applying a molding compound over the substantially conformal dielectric thin film coating.

### Claim 2 (depends on 1)

The method as in claim 1, further comprising:
bonding wires from the second side of the die to the first side of the package substrate before forming the substantially conformal dielectric thin film coating;
encasing the bonded wires in the substantially conformal dielectric thin film coating when the coating is formed over the die;
attaching solder balls to a second side of the package substrate after applying the molding compound; and
singulating the package substrate after attaching the solder balls.

### Claim 3 (depends on 1)

The method as in claim 1, further comprising:
underfilling a region between the first side of the die and the first side of the package substrate before forming the substantially conformal dielectric thin film coating;
encasing the underfill in the substantially conformal dielectric thin film coating when the coating is formed over the die;
attaching solder balls to a second side of the package substrate after applying the molding compound; and
singulating the package substrate after attaching the solder balls.

### Claim 4 (depends on 1)

The method as in claim 1, wherein forming the substantially conformal dielectric thin film coating further comprises conformally depositing, with vapor phase deposition process performed at approximately 25° C., a film to a thickness of between 10 nm and 300 nm.

### Claim 5 (depends on 4)

The method as in claim 4, wherein a poly(para-xylene) is deposited with a sub-atmospheric chemical vapor deposition (CVD) process.

### Claim 6 (depends on 4)

The method as in claim 4, wherein a material comprising primarily alumina is deposited with an atomic layer deposition (ALD) process.

### Claim 7 (depends on 4)

The method as in claim 4, wherein at least one of a polyimide, a polyalkene, or BCB is deposited with a sub-atmospheric chemical vapor deposition (CVD) process.

### Claim 8 (depends on 1)

The method as in claim 1, wherein forming the conformal dielectric thin film coating further comprises:
spraying an epoxy, a room temperature vulcanized (RTV) silicone, a fluorinated silicone, a fluorinated acrylic or a polyurethane.

### Claim 9 (depends on 8)

The method as in claim 8, wherein the spraying is an aerosol deposition process forming the conformal dielectric thin film coating to a thickness of between 1 μm and 10 μm.

### Claim 10

A method of packaging a memory chip, comprising:
attaching, with a first die attach material, a first memory chip to a first side of a package substrate;
bonding a first wire from a first bond pad on the first memory chip to a second bond pad on the first side of the package substrate;
attaching, with a second die attach material, a second memory chip to the first memory chip;
bonding a second wire from a third bond pad on the second memory chip to a fourth bond pad on the first side of the package substrate;
forming a substantially conformal dielectric thin film coating over both the first and second memory chip stack, adjacent to the first and second die attach materials, over the second and fourth bond pad, and encasing the first and second bonded wires;
applying a molding compound over the substantially conformal dielectric thin film coating to surround the substantially conformal dielectric thin film encasing the first and second bonding wires.

### Claim 11 (depends on 10)

The method as in claim 10, wherein forming the substantially conformal dielectric thin film coating further comprises vapor phase deposition of a poly(para-xylene) or alumina to a thickness of approximately 10 nm to 300 nm.

### Claim at position 12

12-20. (canceled)
