# US 2010/0164074 A1 · Dielectric separator layer

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- Number: US 2010/0164074 A1
- Document ID: US20100164074A1
- Status: Published application
- Kind: A1
- Application number: 12/317,839
- Filed: 2008-12-30
- Published: 2010-07-01
- Earliest claimed: 2008-12-30
- Assignees: Intel Corporation
- Inventors: Sean King
- Web page: https://patentgrep.com/patent/US20100164074A1

## CPC

- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10P 70/23: {during, before or after processing of insulating materials}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/085: {involving intermediate temporary filling with material}
- H10W 20/095: {by irradiating with electromagnetic or particle radiation (plasma treatment H10W20/096)}
- H10W 20/096: {by contacting with gases, liquids or plasmas}
- H10W 20/46: comprising air gaps
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention describes a method including: providing a substrate; stacking interlevel dielectric layers over said substrate, and separating said interlevel dielectric layers with a dielectric separator layer.

## Claims

### Claim 1

(canceled)

### Claim 2

(canceled)

### Claim 3

A method comprising:
providing a substrate;
stacking interlevel dielectric layers over said substrate; and
separating said interlevel dielectric layers with a dielectric separator layer, wherein said dielectric separator layer comprises a modified lower layer and an upper layer.

### Claim 4 (depends on 3)

The method of claim 3 wherein said upper layer is thicker than said modified lower layer.

### Claim 5 (depends on 3)

The method of claim 3 wherein said modified lower layer comprises SiCH or SiCNH.

### Claim 6 (depends on 3)

The method of claim 3 wherein said upper layer comprises SiCNH or SiNH.

### Claim 7

A method comprising:
providing an inlaid interconnect in an interlevel dielectric layer, said inlaid interconnect comprising a via and an overlying trench;
forming a lower layer over said inlaid interconnect and said interlevel dielectric, the lower layer comprising silicon and carbon;
densifying said lower layer to convert said lower layer to a modified lower layer with a k value of between 3.4 and 6.1;
forming an upper layer over said modified lower layer, the upper layer being at least five times as thick as the lower layer and having a k value between 4.3 and 7.0;
forming a second interlevel dielectric layer on the upper layer, the second interlevel dielectric layer having a thickness at least twenty times as thick as the upper layer and having a k value less than 2.75;
etching the second interlevel dielectric layer to form a via opening, the upper layer acting as an etch stop layer for the etch; and
filling the via opening with a barrier layer and conductor layer, the barrier layer extending from at least the top of the second interlevel dielectric layer to at least the lower layer.

### Claim 8 (depends on 7)

The method of claim 7 further comprising coating and baking a spin-in dielectric to form said interlevel dielectric layer

### Claim 9 (depends on 7)

The method of claim 7 wherein said interlevel dielectric layer is formed with plasma enhanced chemical vapor deposition (PECVD) comprising:
a substrate temperature of about 250-400 degrees Centigrade; and
a reactor pressure of about 20-250 Torr.

### Claim 10 (depends on 7)

The method of claim 7 wherein said densifying of said lower layer comprises a plasma pretreatment.

### Claim 11 (depends on 10)

The method of claim 10 wherein said plasma pretreatment removes Carbon from a top surface of said lower layer.

### Claim 12

A structure comprising:
a substrate;
an interlevel dielectric layer disposed over said substrate;
an opening disposed in said interlevel dielectric layer layer;
a conductor disposed in said opening; and
a dielectric separator layer disposed over said conductor and said interlevel dielectric layer, the dielectric separator layer comprising a lower layer and an upper layer, the lower layer having a k value between 3.4 and 6.1, the upper layer being at least five times as thick as the lower layer and having a k value between 4.3 and 7.0;
a second interlevel dielectric layer on the upper layer, the second interlevel dielectric layer having a thickness at least twenty times as thick as the upper layer and having a k value less than 2.75;
a barrier layer and conductor layer extending from at least a top of the second interlevel dielectric layer to at least the lower layer.

### Claim 13

(canceled)

### Claim 14 (depends on 12)

The structure of claim 12 wherein the lower layer is a modified lower layer

### Claim 15

(canceled)

### Claim 16 (depends on 12)

The structure of claim 12 wherein said interlevel dielectric layer is porous and comprises a total porosity of about 0.60-0.75.

### Claim 17 (depends on 12)

The structure of claim 12 wherein said interlevel dielectric layer is porous and comprises closed pores with an equivalent diameter of about 2-6 nm.

### Claim 18 (depends on 12)

The structure of claim 12 wherein said interlevel dielectric layer comprises a thickness of about 100-500 nanometers.

### Claim 19 (depends on 12)

The structure of claim 12 wherein said interlevel dielectric layer comprises an effective k value of 1.25-1.75.

### Claim 20 (depends on 12)

The structure of claim 12 wherein said porous ILD layer comprises a Young's modulus of elasticity of 0.8-2.0 GigaPascals.

### Claim 21 (depends on 12)

The structure of claim 12, wherein the lower layer has a thickness of 1.0 nanometers or less.

### Claim 22 (depends on 7)

The method of claim 7, wherein the lower layer has a thickness of 1.0 nanometers or less.