# US 2010/0164069 A1 · Reducing High-Frequency Signal Loss in Substrates > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2010/0164069 A1 - Document ID: US20100164069A1 - Status: Published application - Kind: A1 - Application number: 12/347,208 - Filed: 2008-12-31 - Published: 2010-07-01 - Earliest claimed: 2008-12-31 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Chewn-Pu Jou; Ho-Hsiang Chen - Web page: https://patentgrep.com/patent/US20100164069A1 ## CPC - H10W 44/501: {Inductive arrangements (H10W44/20 takes precedence)} - H10D 84/00: Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers - H10W 20/497: {Inductive arrangements or effects of, or between, wiring layers} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract An integrated circuit structure includes a semiconductor substrate of a first conductivity type; and a depletion region in the semiconductor substrate. A deep well region is substantially enclosed by the depletion region, wherein the deep well region is of a second conductivity type opposite the first conductivity type. The depletion region includes a first portion directly over the deep well region and a second portion directly under the deep well region. An integrated circuit device is directly over the depletion region. ## Claims ### Claim 1 An integrated circuit structure comprising: a semiconductor substrate of a first conductivity type; a depletion region in the semiconductor substrate; a deep well region substantially enclosed by the depletion region, wherein the deep well region is of a second conductivity type opposite the first conductivity type, and wherein the depletion region comprises a first portion directly over the deep well region and a second portion directly under the deep well region; and an integrated circuit device directly over the depletion region. ### Claim 2 (depends on 1) The integrated circuit structure of claim 1, wherein the deep well region is of n-type, and wherein a portion of the semiconductor substrate directly over the deep well region and a portion of the semiconductor substrate directly under the deep well region are of p-type. ### Claim 3 (depends on 2) The integrated circuit structure of claim 2 further comprising a voltage source connected to the deep well region, wherein the voltage source is configured to provide a positive voltage to the deep well region. ### Claim 4 (depends on 3) The integrated circuit structure of claim 3, wherein the positive voltage is a positive power supply voltage of a core circuit. ### Claim 5 (depends on 3) The integrated circuit structure of claim 3, wherein the positive voltage is a positive power supply voltage of an input/output circuit. ### Claim 6 (depends on 1) The integrated circuit structure of claim 1, wherein the integrated circuit device is a radio frequency (RF) transformer. ### Claim 7 (depends on 6) The integrated circuit structure of claim 6 further comprising a dielectric layer over the semiconductor substrate and spacing the depletion region apart from the RF transformer. ### Claim 8 (depends on 1) The integrated circuit structure of claim 1, wherein the integrated circuit device is a diode. ### Claim 9 (depends on 8) The integrated circuit structure of claim 8, wherein the diode is a junction diode comprising a first well region in the semiconductor substrate, and a second well region in the first well region, wherein the first well region and the second well region are of opposite conductivity types. ### Claim 10 (depends on 8) The integrated circuit structure of claim 8, wherein the diode is a FinFET diode comprising a first fin region over the semiconductor substrate, and a second fin region over the semiconductor substrate and contacting the first fin region, and wherein the first fin region and the second fin region are of opposite conductivity types. ### Claim 11 (depends on 8) The integrated circuit structure of claim 8, wherein the diode is a Schottky diode. ### Claim 12 (depends on 1) The integrated circuit structure of claim 1, wherein the depletion region has an area substantially no less than an area of the integrated circuit device. ### Claim 13 (depends on 1) The integrated circuit structure of claim 1, wherein the deep well region comprises a plurality of deep well fingers parallel to each other. ### Claim 14 (depends on 13) The integrated circuit structure of claim 13, wherein widths of the plurality of deep well fingers are close to a minimum width of a technology for forming the integrated circuit structure. ### Claim 15 An integrated circuit structure comprising: a semiconductor substrate of a first conductivity type; a deep well region in the semiconductor substrate and having a top surface lower than a top surface of the semiconductor substrate, wherein the deep well region is of a second conductivity type opposite the first conductivity type; a voltage source connected to the deep well region; a radio frequency (RF) transformer directly over the deep well region; and a dielectric layer spacing the (RF) transformer apart from the top surface of the semiconductor substrate. ### Claim 16 (depends on 15) The integrated circuit structure of claim 15, wherein the first conductivity is p-type, the second conductivity type is n-type, and wherein the voltage source is configured to provide a positive voltage. ### Claim 17 (depends on 16) The integrated circuit structure of claim 16, wherein the voltage source is configured to provide a positive power supply voltage of a core circuit to the deep well region. ### Claim 18 (depends on 15) The integrated circuit structure of claim 15, wherein the first conductivity type is n-type, the second conductivity type is p-type, and wherein the voltage source is configured to provide a negative voltage. ### Claim 19 (depends on 15) The integrated circuit structure of claim 15 further comprising a depletion region substantially encircling the deep well region, wherein the depletion region extends from a top surface of the deep well region to the top surface of the semiconductor substrate, and wherein the depletion region has an area substantially no less than an area of the RF transformer. ### Claim 20 (depends on 19) The integrated circuit structure of claim 19, wherein the area of the depletion region is greater than the area of the RF transformer, and wherein the depletion region laterally extends beyond respective edges of the RF transformer in substantially all lateral directions. ### Claim 21 (depends on 19) The integrated circuit structure of claim 19, wherein the deep well region comprises a plurality of deep well fingers, with the depletion region extending between the plurality of deep well fingers. ### Claim 22 An integrated circuit structure comprising: a semiconductor substrate of a first conductivity type; a diode; a deep well region in the semiconductor substrate and directly under the diode, wherein the deep well region is of a second conductivity type opposite the first conductivity type; and a depletion region comprising a first portion directly over the deep well region and a second portion directly under the deep well region, wherein the first portion spaces the deep well region apart from the diode. ### Claim 23 (depends on 22) The integrated circuit structure of claim 22, wherein the first portion and the second portion of the depletion region are potions of a continuous depletion region substantially enclosing the deep well region. ### Claim 24 (depends on 22) The integrated circuit structure of claim 22, wherein the diode is a junction diode comprising a first well region in the semiconductor substrate, and a second well region in the first well region, wherein the first well region and the second well region are of opposite conductivity types. ### Claim 25 (depends on 22) The integrated circuit structure of claim 22, wherein the depletion region extends to a top surface of the semiconductor substrate, wherein the diode is a FinFET diode comprising a first fin region over the semiconductor substrate, and a second fin region over the semiconductor substrate and contacting the first fin region, and wherein the first fin region and the second fin region are of opposite conductivity types. ### Claim 26 (depends on 22) The integrated circuit structure of claim 22, wherein the diode is a Schottky diode comprising: a doped semiconductor region in the semiconductor substrate; and a metal contact plug contacting the doped semiconductor region. ### Claim 27 (depends on 22) The integrated circuit structure of claim 22 further comprising a voltage source connected to the deep well region and configured to provide a positive voltage for generating the depletion region. ### Claim 28 (depends on 22) The integrated circuit structure of claim 22, wherein the first conductivity type is n-type, the second conductivity type is p-type, and wherein the voltage source is configured to provide a negative voltage. ### Claim 29 (depends on 22) The integrated circuit structure of claim 22, wherein the depletion region has an area substantially no less than an area of the diode. ### Claim 30 (depends on 29) The integrated circuit structure of claim 29, wherein the area of the depletion region is greater than the area of the diode, and wherein the depletion region substantially laterally extends beyond respective edges of the diode in all lateral directions. ### Claim 31 (depends on 22) The integrated circuit structure of claim 22, wherein the deep well region comprises a plurality of deep well fingers, with the depletion region extending to between the plurality of deep well fingers.