# US 2010/0164019 A1 · Method of manufacturing nonvolatile memory device

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- Number: US 2010/0164019 A1
- Document ID: US20100164019A1
- Status: Published application
- Kind: A1
- Application number: 12/632,155
- Filed: 2009-12-07
- Published: 2010-07-01
- Earliest claimed: 2008-12-26
- Inventors: Heedon Jeong
- Web page: https://patentgrep.com/patent/US20100164019A1

## CPC

- H10B 43/30: characterised by the memory core region
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 30/696: {having at least one additional gate, e.g. program gate, erase gate or select gate}
- H10D 64/037: {comprising charge-trapping insulators}
- H10B 43/40: characterised by the peripheral circuit region
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of manufacturing a nonvolatile memory (NVM) device having a memory gate and a selection gate. A method of manufacturing a NVM device may include a spacer poly formed on and/or over a surface of a substrate including a memory gate. A method of manufacturing a NVM device may include a sacrificing film formed on and/or over a surface of a spacer poly. A method of manufacturing a NVM device may include an etch-back process performed to form a selection gate. The thickness of a memory gate may be minimized. A bridge between a selection gate and a source/drain may be minimized.

## Claims

### Claim 1

A method comprising:
forming a spacer poly over a surface of a substrate comprising a memory gate;
forming a sacrificing material over a surface of said spacer poly;
removing said sacrificing material by etching to expose a surface of said spacer poly and to form a sacrificing film to etch-back around a sidewall of said memory gate;
removing said spacer poly by etching such that a surface of the substrate is exposed and such that a portion of said spacer poly remain over a source forming region at a sidewall of said memory gate below said sacrificing film;
removing said sacrificing film to form a selection gate at a side surface of said memory gate;
forming a source/drain region over a predetermined region of the substrate; and
forming metal wires connected with said source/drain region through contact plugs.

### Claim 2 (depends on 1)

The method of claim 1, wherein the thickness of said spacer poly is between approximately 2000Å and 2500Å.

### Claim 3 (depends on 1)

The method of claim 1, wherein said sacrificing material comprises at least one of a nitride and an oxide.

### Claim 4 (depends on 3)

The method of claim 3, wherein forming said sacrificing material comprises chemical vapor deposition.

### Claim 5 (depends on 3)

The method of claim 3, wherein the thickness of said sacrificing material is between approximately 200Å and 300Å.

### Claim 6 (depends on 1)

The method of claim 1, wherein removing said sacrificing material comprises an etch-back process.

### Claim 7 (depends on 1)

The method of claim 1, wherein removing said spacer poly comprises an etch-back process.

### Claim 8 (depends on 1)

The method of claim 1, wherein removing said sacrificing film comprises wet etching.

### Claim 9 (depends on 1)

The method of claim 1, wherein forming said source/drain region comprises:
removing said spacer poly formed over said source forming region and performing ion implantation to form a source ion implanted layer;
selectively exposing a drain forming region and performing ion implantation to form a drain ion implanted layer;
forming a lightly doped drain spacer at a sidewall of said memory gate and said selection gate; and
implanting high-concentration ions over said source ion implanted region and said drain ion implanted layers to form said source/drain region.

### Claim 10 (depends on 9)

The method of claim 9, comprising:
forming salicide over at least one of said memory gate, said selection gate and said source/drain region;
forming an interlayer insulating film over a surface of the substrate;
selectively removing a portion of said interlayer insulating film to form contact plugs; and
forming metal wires connected said source/drain region.

### Claim 11 (depends on 10)

The method of claim 10, wherein implanting said high-concentration ions and forming said salicide are performed simultaneously with high-concentration ion implantation and salicide formation of a logic device.

### Claim 12 (depends on 9)

The method of claim 9, wherein said drain ion implanted layer is formed simultaneously with a drain region of a logic device.

### Claim 13

An apparatus comprising:
a memory gate;
a selection gate at a sidewall of said memory gate and spaced apart from said memory gate by a buffer oxide film;
a lightly doped drain spacer at said sidewall of said memory gate and said selection gate;
a source/drain region;
salicide over at least one of said memory gate, said selection gate and said source/drain region;
an interlayer insulating film over a surface of the substrate; and
contact plugs and metal wires connected to said source/drain region.

### Claim 14 (depends on 13)

The apparatus of claim 13, wherein said source/drain region comprise high-concentration ions implanted over a source ion implanted layer and a drain ion implanted layer.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein said drain ion implanted layer is formed simultaneously with a drain region of a logic device.

### Claim 16 (depends on 13)

The apparatus of claim 13, wherein implanting said high-concentration ions and forming salicide are performed simultaneously with high-concentration ion implantation and salicide formation of a logic device.

### Claim 17 (depends on 13)

The apparatus of claim 13, comprising a nonvolatile memory device

### Claim 18 (depends on 13)

The apparatus of claim 13, wherein said buffer oxide film is disposed between said substrate and said selection gate.

### Claim 19 (depends on 13)

The apparatus of claim 13, comprising a plurality of at least one of said memory gate and said selection gate.

### Claim 20 (depends on 19)

The apparatus of claim 19, where said plurality is disposed between a device isolation film.