# US 2010/0164012 A1 · Semiconductor device and method of manufacturing the same

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- Number: US 2010/0164012 A1
- Document ID: US20100164012A1
- Status: Published application
- Kind: A1
- Application number: 12/649,261
- Filed: 2009-12-29
- Published: 2010-07-01
- Earliest claimed: 2008-12-31
- Assignees: Dongbu HiTek Co., Ltd.
- Inventors: Yeo-Cho Yoon
- Web page: https://patentgrep.com/patent/US20100164012A1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/0109: {the at least one component covered by H10D12/00 or H10D30/00 being a MOS device}
- H10D 84/401: {Combinations of FETs or IGBTs with BJTs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a semiconductor substrate including a CMOS region and a bipolar region, a first N well and a first P well in the CMOS region, a PMOS device in the first N well and an NMOS device in the first P well, a deep P well in the bipolar region, a second N well in the deep P, a second isolation layer between the deep P well and the second N well, a third isolation in the second N well, a collector in the second N well between the second and third isolation layers, and a base formed in the second N well and having a bottom surface including first type impurities to contact the emitter.

## Claims

### Claim 1

An apparatus comprising:
a semiconductor substrate including a CMOS region and a bipolar region;
a first N well and a first P well formed in the CMOS region and separated from each other by a first isolation layer;
a PMOS device formed in the first N well and an NMOS device formed in the first P well;
a deep P well formed in the bipolar region;
a second N well formed in the deep P well to expose a portion of the deep P well;
a second isolation layer formed between the deep P well and the second N well to define an emitter region;
an emitter having second type impurities formed in the deep P well;
a third isolation layer defining base and collector regions formed in the second N well;
a collector having second type impurities formed in the second N well between the second and third isolation layers; and
a base formed having first type impurities formed in the second N well at one side of the third isolation layer and having a bottom surface which contacts the emitter.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the emitter includes P type impurities.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the base includes N type impurities.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the collector includes P type impurities.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the emitter, the base and the collector form a PNP bipolar transistor.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the emitter, the base and the collector form a PNP bipolar transistor.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the collector is formed in the second N well between the second and third isolation layers.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein the base is formed in the second N well in such a manner that the base contacts the collector.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the emitter is formed in the deep P well in such a manner that the emitter contacts the base.

### Claim 10 (depends on 1)

The apparatus of claim 1, further comprising a deep N well formed below the deep P well in the bipolar region.

### Claim 11

A method comprising:
forming a semiconductor substrate including a CMOS region and a bipolar region;
forming a first isolation layer in the CMOS region and second and third isolation layers in the bipolar region;
forming a first P well at one side of the first isolation layer and a first N well at an opposite side of the first isolation layer;
forming a deep P well in the bipolar region and a second N well in the deep P well corresponding to one side of the second isolation layer;
forming a first gate in the first N well and a second gate in the first P well;
forming a first source/drain by implanting second type impurities into the first N well, and an emitter and a collector by implanting second type impurities into the deep P well and the second N well at both sides of the second isolation layer; and then
forming a second source/drain by implanting the second type impurities into the first P well, and a base by implanting the second type impurities into the second N well at one side of the third isolation layer.

### Claim 12 (depends on 11)

The method of claim 11, further comprising forming a deep N well at a deep region of the bipolar region before forming the deep P well.

### Claim 13 (depends on 11)

The method of claim 11, wherein the emitter and the collector include P type impurities and the base includes N type impurities so that a PNP bipolar transistor is formed.

### Claim 14 (depends on 11)

The method of claim 11, further comprising:
forming a first photoresist pattern over the semiconductor substrate to selectively expose the first N well and portions of the deep P well and the second N well at both sides of the second isolation layer; and then
forming first LDD regions in the first N well corresponding to both sides of the first gate, and second type shallow doped layers at a portion of the second N well and the deep P well using the first photoresist pattern as an ion implantation mask, after forming the first and second gates.

### Claim 15 (depends on 14)

The method of claim 14, wherein forming the first source/drain in the first N well and the forming of the emitter and the collector in emitter and collector regions comprises:
forming a third photoresist pattern using a mask identical to a mask of the first photoresist pattern; and then
forming the first source/drain below the first LDD region and a second type deep doped layer below the second type shallow doped layer using the third photoresist pattern as an ion implantation mask.

### Claim 16 (depends on 11)

The method of claim 11, further comprising:
forming a second photoresist pattern to expose the first P well of the semiconductor substrate and the second N well at one side of the third isolation layer; and
forming second LDD regions at the first P well corresponding to both sides of the second gate, and a first type shallow doped layer at a portion of the second N well by using the second photoresist pattern as an ion implantation mask, after forming the first and second gates.

### Claim 17 (depends on 16)

The method of claim 16, wherein forming of the second source/drain in the first P well, and the base in the base region comprises:
forming a fourth photoresist pattern using a mask identical to a mask of the second photoresist pattern; and then
forming the second source/drain below the second LDD region and a first type deep doped layer below the first type shallow doped layer using the fourth photoresist pattern as an ion implantation mask.

### Claim 18 (depends on 5)

The method of claim 5, further comprising:
forming an interlayer dielectric layer; and then
forming an emitter electrode, a collector electrode and a base electrode connected with the emitter, the collector, and the base, respectively, through the interlayer dielectric layer, after forming the base in the base region.

### Claim 19

An apparatus comprising:
a semiconductor substrate including a CMOS region and a bipolar region;
a first isolation layer formed in the semiconductor substrate;
a first N well formed in the CMOS region;
a first P well formed in the CMOS region and separated from the first N well by the first isolation layer;
a PMOS device formed in the first N well;
an NMOS device formed in the first P well;
a deep P well formed in the bipolar region;
a second N well formed in the deep P well;
a second isolation layer formed between the deep P well and the second N well to define an emitter region;
an emitter formed in the deep P well;
a third isolation layer formed in the second N well defining a base region and a collector region;
a collector formed in the second N well between the second and third isolation layers; and
a base formed in the second N well at one side of the third isolation layer, the base contacting the emitter.

### Claim 20 (depends on 19)

The apparatus of claim 19, wherein the emitter, the base and the collector form a PNP bipolar transistor.