# US 2010/0163979 A1 · True csp power mosfet based on bottom-source ldmos

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- Number: US 2010/0163979 A1
- Document ID: US20100163979A1
- Status: Published application
- Kind: A1
- Application number: 12/345,467
- Filed: 2008-12-29
- Published: 2010-07-01
- Earliest claimed: 2008-12-29
- Assignees: Alpha and Omega Semiconductor Incorporated
- Inventors: Francois Hebert
- Web page: https://patentgrep.com/patent/US20100163979A1

## CPC

- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/664: {Inverted VDMOS transistors, i.e. source-down VDMOS transistors}
- H10D 64/254: {for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/111: {Field plates}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/5524: {comprising aluminium [Al]}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/9232: {with additional elements interposed between layers}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package may comprise a semiconductor substrate, a MOSFET device having a plurality cells formed on the substrate, and a source region common to all cells disposed on a bottom of the substrate. Each cell comprises a drain region on a top of the semiconductor device, a gate to control a flow of electrical current between the source and drain regions, a source contact proximate the gate; and an electrical connection between the source contact and source region. At least one drain connection is electrically coupled to the drain region. Source, drain and gate pads are electrically connected to the source region, drain region and gates of the devices. The drain, source and gate pads are formed on one surface of the semiconductor package. The cells are distributed across the substrate, whereby the electrical connections between the source contact of each device and the source region are distributed across the substrate.

## Claims

### Claim 1

A semiconductor chip scale package (CSP) comprising:
a semiconductor substrate;
a semiconductor device including a discrete metal oxide semiconductor field effect transistor (MOSFET) having a plurality of cells formed in an active area of the semiconductor substrate;
a source region disposed on a bottom of the substrate that is common to all the cells in the plurality,
wherein each cell in the plurality comprises:
a drain region disposed on a top of the semiconductor device;
a gate configured to control a flow of electrical current between the source region and the drain region when a voltage is applied to the gate;
a source contact located proximate the gate; and
an electrical connection formed through the substrate between the source contact and the source region;
at least one drain pad electrically coupled to the drain regions;
at least one source pad electrically connected to the source region wherein the source pad is biased to the substrate;
at least one gate pad electrically coupled to the gates;
a drain metal substantially covering the entire active area;
a buried body-source short structure connected to the source pad, wherein the buried body-source short structure runs beneath the drain metal;
wherein the drain, source and gate pads are formed on one surface of the semiconductor device;
wherein the plurality of cells are distributed across the substrate, whereby the electrical connections formed between the source contact of each semiconductor device and the source region are distributed across the substrate;
wherein the drain pads are formed on the active area of the semiconductor package;
wherein the source and gate pads are formed on a termination area of the semiconductor package that is outside the active area.

### Claim 2 (depends on 1)

The semiconductor chip scale package of claim 1, wherein the body-source short structure is a buried gate shield.

### Claim 3 (depends on 1)

The semiconductor chip scale package of claim 1, wherein the body-source short structure is a buried conductive plug.

### Claim 4 (depends on 1)

The semiconductor chip scale package of claim 1, wherein the body-source short structure distributes the source throughout the semiconductor device.

### Claim 5 (depends on 1)

The semiconductor chip scale package of claim 1 further comprising a gate ring disposed at a periphery of the semiconductor package, configured for interconnection between the gate pad and the gate region of the semiconductor device.

### Claim 6 (depends on 5)

The semiconductor chip scale package of claim 5 further comprising a metallized substrate ring disposed at the periphery of the semiconductor package, configured to directly connect to the source pad.

### Claim 7 (depends on 1)

The semiconductor chip scale package of claim 1, wherein each cell further comprises a conductive plug configured to electrically connect the drain region to the drain metal.

### Claim 8 (depends on 7)

The semiconductor chip scale package of claim 7 wherein the MOSFET is a bottom-source LDMOS device.

### Claim 9 (depends on 8)

The semiconductor chip scale package of claim 8, wherein the electrical connection formed between the source contact of each cell of the bottom-source LDMOS device and the source region comprises a top source region, the substrate, and a combined sinker-channel region in an epitaxial layer, wherein the combined sinker-channel region functions as a sinker that electrically connects the substrate to the top source region and as a body region where a MOSFET channel is formed, and wherein the buried body-source short structure shorts the top source region to the sinker-channel region.

### Claim 10 (depends on 9)

The semiconductor chip scale package of claim 9, wherein the bottom-source LDMOS device further comprises a drift region disposed under the gate region and at a distance away from the source region and extending to and encompassing the drain region.

### Claim 11 (depends on 10)

The semiconductor chip scale package of claim 10, wherein the combined sinker-channel region extending below the drift region and having a dopant conductivity opposite to and compensating the drift region for a reduced source-drain capacitance.

### Claim 12 (depends on 11)

The semiconductor chip scale package of claim 11, wherein the bottom-source LDMOS device wherein the buried body-source short structure comprises a buried gate shield layer comprising a conductive layer disposed above the gate region, the source region and the body region.

### Claim 13 (depends on 12)

The semiconductor chip scale package of claim 12, wherein the buried gate shield layer comprises a Titanium Nitride or Titanium Silicide metallization.

### Claim 14 (depends on 12)

The semiconductor chip scale package of claim 12 wherein the source pad is located over the buried gate shield layer.

### Claim 15 (depends on 14)

The semiconductor chip scale package of claim 14 wherein the buried gate shield layer distributes the source throughout the semiconductor device.

### Claim 16 (depends on 14)

The semiconductor chip scale package of claim 14, further comprising one or more conductive plugs to connect the source pad to the buried shield gate layer.

### Claim 17 (depends on 1)

The semiconductor chip scale package of claim 1, wherein the MOSFET comprises an inverted-trench grounded-source vertical channel MOSFET device.

### Claim 18 (depends on 17)

The semiconductor chip scale package of claim 17, wherein each cell of the inverted-trench grounded-source vertical channel MOSFET device further comprises:
a vertical current conducting channel between the source region and the drain region controlled by a vertical sidewall gate region disposed on sidewalls of a trench and padded by a gate oxide layer attached to the sidewalls of the trench;
wherein the buried body-source short structure is a buried conductive plug extending downwardly from a bottom surface of the trench for electrically shorting a body region in the semiconductor substrate to a source region disposed at a bottom of the trench.

### Claim 19 (depends on 18)

The semiconductor chip scale package of claim 18, wherein the buried conductive plug in each cell is configured to distribute the source among the cells in the plurality.

### Claim 20 (depends on 18)

The semiconductor chip scale package of claim 18, wherein the conductive plug in each cell comprises a silicide of Titanium, Cobalt or Tungsten.

### Claim 21 (depends on 18)

The semiconductor chip scale package of claim 18 wherein each cell of the inverted-trench grounded-source vertical channel MOSFET device further comprises:
a doped body region disposed in the semiconductor substrate and surrounding a lower portion of the trench encompassing the source region wherein the doped body region includes the channel along sidewalls of the trench;
a drift region disposed near the top surface of the substrate surrounding an upper portion of the trench and encompassing the drain region; and
a link region disposed below the drift region and extending downwardly to the doped channel region for linking the drift region and the doped channel region.

### Claim 22 (depends on 18)

The semiconductor chip scale package of claim 18 further comprising a gate metal disposed in a termination and a plurality of gate runners, each gate runner providing an electrical connection between the gate region of a cell in the plurality and the gate metal disposed in the termination area.

### Claim 23

A method for manufacturing a semiconductor chip scale package (CSP) comprising:
forming a semiconductor substrate;
forming a plurality of cells on an active area of the semiconductor substrate, each cell comprising a gate region, a source region disposed on a bottom of the semiconductor device, a drain region disposed on a top of the semiconductor device and distributed substrate connections for the source region formed within every semiconductor device;
forming a common drain metal on the plurality of the semiconductor devices;
forming a buried body-source short structure which runs underneath the common drain metal and which is connected to the source region and the source pad;
forming at least one drain pad on top of the common drain metal; and
forming at least one source pad and one at least one gate pad on a termination area of the semiconductor substrate, wherein the source pad is placed over the buried body-source short structure;
wherein the drain, source and gated pads are on one surface of the semiconductor package.

### Claim 24 (depends on 23)

The method of claim 23 wherein the buried body-source short structure distributes the source throughout the plurality of cells.