# US 2010/0163976 A1 · Semiconductor Device Having Saddle Fin Transistor and Method for Fabricating the Same

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- Number: US 2010/0163976 A1
- Document ID: US20100163976A1
- Status: Published application
- Kind: A1
- Application number: 12/494,567
- Filed: 2009-06-30
- Published: 2010-07-01
- Earliest claimed: 2008-12-26
- Assignees: Hynix Semiconductor Inc.
- Inventors: Jin Yul LEE; Dong Seok KIM
- Web page: https://patentgrep.com/patent/US20100163976A1

## CPC

- H10D 30/023: {having multiple independently-addressable gate electrodes influencing the same channel (manufacture or treatment of dual gate TFTs H10D30/031)}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/056: {the transistor being a FinFET}
- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method for fabricating a semiconductor device includes forming a pad nitride layer that exposes an isolation region over a cell region of a semiconductor substrate; forming a trench in the isolation region of the semiconductor substrate; forming an isolation layer within the trench; etching an active region of the semiconductor substrate by a certain depth to form a recessed isolation region; etching the isolation layer by a certain depth to form a recessed isolation region; depositing a gate metal layer in the recessed active region and the recessed isolation region to form a gate of a cell transistor; forming an insulation layer over an upper portion of the gate; removing the pad nitride layer to expose a region of the semiconductor substrate to be formed with a contact plug; and depositing a conductive layer in the region of the semiconductor substrate to form a contact plug.

## Claims

### Claim 1

A semiconductor device having a saddle fin transistor, comprising:
a trench having a selected depth in an active region of a semiconductor substrate;
an isolation layer surrounding the active region and having a recessed isolation region that forms a saddle type fin structure in the active region;
a saddle fin gate of a cell transistor buried in the trench and the recessed isolation region;
an insulation layer over the saddle fin gate, the insulation layer exposing a region of the semiconductor substrate; and
a contact plug in the region exposed by the insulation layer.

### Claim 2 (depends on 1)

The semiconductor device having a saddle fin transistor of claim 1, wherein a depth of the recessed isolation region is in a range of 1,200 to 2,000 Å.

### Claim 3 (depends on 1)

The semiconductor device having a saddle fin transistor of claim 1, wherein the saddle fin gate comprises
a gate insulation layer on a surface of the trench; and
a gate metal layer in the recessed isolation region and over the gate insulation layer in the active region.

### Claim 4 (depends on 3)

The semiconductor device having a saddle fin transistor of claim 3, wherein the saddle fin gate further comprises a doped polysilicon layer between the gate insulation layer and the gate metal layer.

### Claim 5 (depends on 1)

The semiconductor device having a saddle fin transistor of claim 1, wherein the contact plug comprises a polysilicon or metal layer.

### Claim 6

A semiconductor device having a saddle fin transistor, comprising:
a semiconductor substrate having a cell region and a peripheral circuit region;
a saddle fin gate disposed in the cell region under a surface of the semiconductor substrate;
a stack type gate disposed over the peripheral circuit region of the semiconductor substrate;
an insulation layer covering the saddle fin gate, the insulation layer exposing a contact region in the cell region; and
a contact plug in the contact region exposed by the insulation layer in the cell region.

### Claim 7 (depends on 6)

The semiconductor device having a saddle fin transistor of claim 6, wherein the saddle fin gate comprises
an inner wall of a trench having a selected depth in an active region of the cell region;
a gate insulation layer along a surface of a recessed isolation region that forms a saddle fin structure; and
a gate metal layer in the trench and the recessed isolation region.

### Claim 8 (depends on 7)

The semiconductor device having a saddle fin transistor of claim 7, wherein the saddle fin gate further comprises a doped polysilicon layer between the gate insulation layer and the gate metal layer.

### Claim 9 (depends on 6)

The semiconductor device having a saddle fin transistor of claim 6, wherein the stack type gate comprises a gate insulation layer, a gate conductive layer, a metal electrode layer and a hard mask, which are sequentially stacked over the peripheral circuit region of the semiconductor substrate.

### Claim 10 (depends on 6)

The semiconductor device having a saddle fin transistor of claim 6, wherein the contact plug comprises the same material as a gate conductive layer of the stack type gate in the peripheral circuit region.

### Claim 11 (depends on 6)

The semiconductor device having a saddle fin transistor of claim 6, further comprising a nitride layer spacer on a side face of the insulation layer.

### Claim 12

A method for fabricating a semiconductor device having a saddle fin transistor, comprising:
forming a pad nitride layer that exposes an isolation region over a cell region of a semiconductor substrate;
forming a trench in the isolation region of the semiconductor substrate;
forming an isolation layer within the trench;
etching an active region of the semiconductor substrate by a selected depth to form a recessed active region;
etching the isolation layer by a selected depth to form a recessed isolation region;
depositing a gate metal layer in the recessed active region and the recessed isolation region to form a gate of a cell transistor;
forming an insulation layer over an upper portion of the gate;
removing the pad nitride layer to expose a region of the semiconductor substrate to be formed with a contact plug; and
depositing a conductive layer in the region of the semiconductor substrate to form a contact plug.

### Claim 13 (depends on 12)

The method of claim 12, further comprising
forming a gate insulation layer over surfaces of the recessed active region and the recessed isolation region before forming the gate metal layer; and
performing an etch back or a chemical mechanical polishing (CMP) followed by an etch back on the gate metal layer.

### Claim 14 (depends on 13)

The method of claim 13, wherein in performing an etch back or a CMP followed by an etch back, a surface of the gate metal layer comes to have the same height as the active region.

### Claim 15 (depends on 13)

The method of claim 13, wherein forming the gate of the cell transistor further comprises forming a polysilicon layer over the gate insulation layer before forming the gate metal layer.

### Claim 16 (depends on 12)

The method of claim 12, wherein forming the insulation layer over the upper portion of the gate further comprises performing an etch back or a CMP to expose the pad nitride layer.

### Claim 17

A method for fabricating a semiconductor device having a saddle fin transistor, comprising:
forming a pad nitride layer that exposes an isolation region over a cell region and a peripheral circuit region of a semiconductor substrate;
forming a trench isolation layer in the isolation region of the semiconductor substrate;
recessing a portion of an active region to be formed with a channel by a selected depth;
recessing a portion of the trench isolation layer to form a saddle fin shape;
forming a saddle fin gate buried under a surface of the semiconductor substrate in the recessed active region;
forming an insulation layer over an upper portion of the saddle fin gate to isolate the saddle fin gate;
removing the pad nitride layer to expose a portion of the semiconductor substrate in the cell region to be formed with a contact plug and the peripheral circuit region of the semiconductor substrate;
forming a gate insulation layer over the peripheral circuit region of the semiconductor substrate;
forming a conductive layer over the cell region;
forming a conductive layer over the peripheral circuit region of the semiconductor substrate; and
etching the conductive layers to form a contact plug in the cell region and a stack type gate in the peripheral circuit region.

### Claim 18 (depends on 17)

The method of claim 17, comprising recessing the portion of the active region and the portion of the trench isolation layer in situ.

### Claim 19 (depends on 17)

The method of claim 17, wherein forming the saddle fin gate comprises:
forming a gate insulation layer over recessed surfaces of the active region and the trench isolation layer;
forming a gate metal layer to bury the recessed portions; and
performing an etch back or a CMP followed by an etch back on the gate metal layer.

### Claim 20 (depends on 19)

The method of claim 19, wherein in performing an etch back or a CMP followed by an etch back, a surface of the gate metal layer comes to have the same height as the active region.

### Claim 21 (depends on 19)

The method of claim 19, wherein forming the saddle fin gate further comprises forming a polysilicon layer over the gate insulation layer before forming the gate metal layer.

### Claim 22 (depends on 17)

The method of claim 17, wherein forming the insulation layer further comprises performing an etch back or a CMP to expose the pad nitride layer.

### Claim 23 (depends on 17)

The method of claim 17, further comprising, before forming the gate insulation layer in the peripheral circuit region,
forming a buffer nitride layer over the resulting product in which the pad nitride layer is removed; and
removing a portion of the buffer nitride layer in the peripheral circuit region.

### Claim 24 (depends on 17)

The method of claim 17, wherein, after forming the conductive layer, a portion of the conductive layer in the peripheral circuit region is etched.

### Claim 25 (depends on 24)

The method of claim 24, comprising forming the conductive layer in the peripheral circuit region by a thickness in a range of 500 to 800 Å.

### Claim 26 (depends on 17)

The method of claim 17, wherein forming the stack type gate in the peripheral circuit region comprises
forming a metal layer over the conductive layer;
forming a hard mask pattern for patterning the stack type gate in the peripheral circuit region over the metal layer; and
etching the metal layer, the conductive layer, and the gate insulation layer using the hard mask pattern as a mask.

### Claim 27 (depends on 17)

The method of claim 17, wherein etching the conductive layer further comprises exposing the insulation layer formed over the stack type gate.

### Claim 28 (depends on 27)

The method of claim 27, wherein the contact plug comprises the same material as the gate conductive layer of the stack type gate formed in the peripheral circuit region.