# US 2010/0163971 A1 · Dielectric Punch-Through Stoppers for Forming FinFETs Having Dual Fin Heights

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- Number: US 2010/0163971 A1
- Document ID: US20100163971A1
- Status: Published application
- Kind: A1
- Application number: 12/347,123
- Filed: 2008-12-31
- Published: 2010-07-01
- Earliest claimed: 2008-12-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Shih-Ting Hung; Cheng-Hung Chang; Chen-Yi Lee; Chen-Nan Yeh; Chen-Hua Yu
- Web page: https://patentgrep.com/patent/US20100163971A1

## CPC

- H10W 10/012: {using local oxidation of silicon [LOCOS]}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 10/13: formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor structure includes a semiconductor substrate having a first portion and a second portion. A first Fin field-effect transistor (FinFET) is formed over the first portion of the semiconductor substrate, wherein the first FinFET includes a first fin having a first fin height. A second FinFET is formed over the second portion of the semiconductor substrate, wherein the second FinFET includes a second fin having a second fin height different from the first fin height. A top surface of the first fin is substantially level with a top surface of the second fin. A punch-through stopper is underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate.

## Claims

### Claim 1

A semiconductor structure comprising:
a semiconductor substrate comprising a first portion and a second portion;
a first Fin field-effect transistor (FinFET) over the first portion of the semiconductor substrate, wherein the first FinFET comprises a first fin having a first fin height; and
a second FinFET over the second portion of the semiconductor substrate, wherein the second FinFET comprises a second fin having a second fin height different from the first fin height, and wherein a first top surface of the first fin is substantially level with a second top surface of the second fin; and
a punch-through stopper underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the first fin is above a first shallow trench isolation (STI) region adjacent the first fin, and the second fin is above a second STI region adjacent the second fin, and wherein the first STI region has a first top surface substantially level with a second top surface of the second STI region.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, wherein a first bottom surface of the first STI region is substantially level with a second bottom surface of the second STI region.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1 further comprising an additional fin directly underlying the first fin, wherein the punch-through stopper electrically disconnects the additional fin from the first fin.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1 further comprising an additional punch-through stopper underlying and adjoining the second fin, wherein the punch-through stopper and the additional punch-through stopper are not level with each other.

### Claim 6 (depends on 5)

The semiconductor structure of claim 5 further comprising an additional fin directly underlying and adjoining the additional punch-through stopper, and wherein the additional fin and the second fin have substantially a same width.

### Claim 7

A semiconductor structure comprising:
a semiconductor substrate;
a first shallow trench isolation (STI) region over the semiconductor substrate and having a first top surface and a first bottom surface;
a second STI region over the semiconductor substrate and having a second top surface substantially level with the first top surface of the first STI region, and a second bottom surface substantially level with the first bottom surface of the first STI region;
a first fin adjacent to, and above, the first STI region;
a second fin adjacent to, and above, the second STI region, wherein the second fin has a top surface substantially level with a top surface of the first fin, and wherein the first fin and the second fin have different fin heights;
a first lower fin underlying and vertically aligned to the first fin, wherein the first lower fin has a bottom surface substantially level with the first bottom surface of the first STI region; and
a first punch-through stopper between and adjoining the first fin and the first lower fin.

### Claim 8 (depends on 7)

The semiconductor structure of claim 7 further comprising:
a first Fin field-effect transistor (FinFET) comprising:
a first gate dielectric on a top surface and sidewalls of the first fin; and
a first gate electrode on the first gate dielectric; and
a second FinFET comprising:
a second gate dielectric on a top surface and sidewalls of the second fin; and
a second gate electrode on the second gate dielectric.

### Claim 9 (depends on 7)

The semiconductor structure of claim 7, wherein the second fin is connected to the semiconductor substrate through an intermediate semiconductor fin.

### Claim 10 (depends on 7)

The semiconductor structure of claim 7 further comprising:
a second lower fin underlying and vertically aligned to the second fin, wherein the second lower fin has a bottom substantially level with the second bottom surface of the second STI region; and
a second punch-through stopper between and adjoining the second fin and the second lower fin, wherein a bottom surface of the second fin is not level with the bottom surface of the first fin.

### Claim 11 (depends on 7)

The semiconductor structure of claim 7, wherein the first top surface of the first STI region is substantially level with a top surface of the first punch-through stopper.

### Claim 12 (depends on 7)

The semiconductor structure of claim 7, wherein the first top surface of the first STI region is lower than a top surface of the first punch-through stopper.

### Claim 13 (depends on 7)

The semiconductor structure of claim 7, wherein the first punch-through stopper comprises an oxide of a semiconductor material of the first fin.

### Claim 14 (depends on 7)

The semiconductor structure of claim 7, wherein the first punch-through stopper has a non-flat top surface.

### Claim 15

A semiconductor structure comprising:
a semiconductor substrate;
a first semiconductor fin above the semiconductor substrate and comprising a first top surface, wherein the first semiconductor fin comprises a first upper portion and a first lower portion;
a first punch-through stopper between and adjoining the first upper portion and the first lower portion of the first semiconductor fin;
a second semiconductor fin above the semiconductor substrate and comprising a second top surface substantially level with the first top surface of the first semiconductor fin, wherein the second semiconductor fin comprise a second upper portion and a second lower portion, and wherein the first upper portion and the second upper portion have different heights; and
a second punch-through stopper between and adjoining the second upper portion and the second lower portion of the second semiconductor fin.

### Claim 16 (depends on 15)

The semiconductor structure of claim 15, wherein the first semiconductor fin is adjacent to a first shallow trench isolation (STI) region, and the second semiconductor fin is adjacent to a second STI region, and wherein the first STI region and the second STI region are at a same vertical level and have a same thickness.

### Claim 17 (depends on 15)

The semiconductor structure of claim 15, wherein a first STI region and a second STI region are formed of a first material, and wherein the first punch-through stopper and the second punch-through stopper are formed of a second material different from the first material.