# US 2010/0163945 A1 · Embedded memory cell and method of manufacturing same

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- Number: US 2010/0163945 A1
- Document ID: US20100163945A1
- Status: Published application
- Kind: A1
- Application number: 12/319,101
- Filed: 2008-12-30
- Published: 2010-07-01
- Earliest claimed: 2008-12-30
- Assignees: Intel Corporation
- Inventors: Jack T. Kavalieros; Niloy Mukherjee; Gilbert Dewey; Dinesh Somasekhar; Brian S. Doyle
- Web page: https://patentgrep.com/patent/US20100163945A1

## CPC

- H10D 1/047: {of conductor-insulator-semiconductor capacitors, e.g. trench capacitors}
- H10B 12/038: {the capacitor being in a trench in the substrate}
- H10B 12/0385: {Making a connection between the transistor and the capacitor, e.g. buried strap}
- H10B 12/0387: {Making the trench}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/373: {the capacitor extending under or around the transistor}
- H10D 1/716: {having vertical extensions}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

An embedded memory cell includes a semiconducting substrate (110), a transistor (120) having a source/drain region (121) at least partially embedded in the semiconducting substrate, and a capacitor (130) at least partially embedded in the semiconducting substrate. The capacitor includes a first electrode (131) and a second electrode (132) that are electrically isolated from each other by a first electrically insulating material (133). The first electrode is electrically connected to the semiconducting substrate and the second electrode is electrically connected to the source/drain region of the transistor.

## Claims

### Claim 1

An embedded memory cell comprising:
a semiconducting substrate;
a transistor having a source/drain region at least partially embedded in the semiconducting substrate; and
a capacitor at least partially embedded in the semiconducting substrate, the capacitor comprising a first electrode and a second electrode that are electrically isolated from each other by a first electrically insulating material,
wherein:
the first electrode is electrically connected to the semiconducting substrate; and
the second electrode is electrically connected to the source/drain region of the transistor.

### Claim 2 (depends on 1)

The embedded memory cell of claim 1 wherein:
the semiconducting substrate has a p-type doping and the source/drain region has an n-type doping.

### Claim 3 (depends on 2)

The embedded memory cell of claim 2 wherein:
the first electrode comprises a metal having a high work function.

### Claim 4 (depends on 2)

The embedded memory cell of claim 2 wherein:
the second electrode comprises a metal having a low work function.

### Claim 5 (depends on 1)

The embedded memory cell of claim 1 wherein:
the capacitor further comprises a second electrically insulating material located between portions of the first electrode and the semiconducting substrate.

### Claim 6 (depends on 1)

The embedded memory cell of claim 1 wherein:
the capacitor further comprises a reaction product between the semiconducting substrate and at least one of the first electrode and the second electrode.

### Claim 7 (depends on 1)

The embedded memory cell of claim 1 wherein:
the first electrically insulating material comprises a high-k dielectric material.

### Claim 8

A method of manufacturing an embedded memory cell, the method comprising:
providing a semiconducting substrate;
forming a transistor having a source/drain region at least partially embedded in the semiconducting substrate;
forming a capacitor having:
a first electrode at least partially embedded in the semiconducting substrate and electrically connected to the semiconducting substrate;
a second electrode at least partially embedded in the semiconducting substrate and electrically connected to the source/drain region; and
a first electrically insulating material that electrically isolates the first electrode and the second electrode from each other.

### Claim 9 (depends on 8)

The method of claim 8 further comprising:
reducing a Schottky barrier height between the first electrode and the semiconducting substrate.

### Claim 10 (depends on 9)

The method of claim 9 wherein:
reducing the Schottky barrier height between the first electrode and the semiconducting substrate comprises:
selecting for the first electrode a metal having a high work function if the semiconducting substrate has a p-type doping; and
selecting for the first electrode a metal having a low work function if the semiconducting substrate has an n-type doping.

### Claim 11 (depends on 8)

The method of claim 8 further comprising:
reducing a Schottky barrier height between the second electrode and the source/drain region.

### Claim 12 (depends on 11)

The method of claim 11 wherein:
reducing the Schottky barrier height between the second electrode and the source/drain region comprises:
selecting for the second electrode a metal having a low work function if the source/drain region has an n-type doping; and
selecting for the second electrode a metal having a high work function if the source/drain region has a p-type doping.

### Claim 13 (depends on 8)

The method of claim 8 further comprising:
forming a second electrically insulating material between portions of the first electrode and the semiconducting substrate.

### Claim 14 (depends on 8)

The method of claim 8 further comprising:
forming a reaction product between the semiconducting substrate and at least one of the first electrode and the second electrode.

### Claim 15 (depends on 14)

The method of claim 14 wherein:
forming the reaction product comprises performing a thermal anneal of the semiconducting substrate and at least one of the first electrode and the second electrode.

### Claim 16

A method of manufacturing an embedded DRAM cell, the method comprising:
providing a semiconducting substrate having a p-type doping;
forming a transistor having a source/drain region at least partially embedded in the semiconducting substrate, the source/drain region having an n-type doping;
forming a trench in the semiconducting substrate;
depositing a high work function metal in the trench such that the high work function metal electrically contacts the semiconducting substrate;
depositing a first electrically insulating material in the trench over the high work function metal; and
depositing a low work function metal in the trench over the first electrically insulating material such that the low work function metal is electrically isolated from the high work function metal and such that the low work function metal electrically contacts the source/drain region.

### Claim 17 (depends on 16)

The method of claim 16 further comprising:
forming a second electrically insulating material between portions of the high work function metal and the semiconducting substrate.

### Claim 18 (depends on 17)

The method of claim 17 further comprising:
forming a reaction product between the semiconducting substrate and at least one of the high work function metal and the low work function metal.

### Claim 19 (depends on 18)

The method of claim 18 wherein:
forming the reaction product comprises performing a thermal anneal of the semiconducting substrate and at least one of the high work function metal and the low work function metal.

### Claim 20 (depends on 19)

The method of claim 19 wherein:
performing the thermal anneal comprises annealing the semiconducting substrate and at least one of the high work function metal and the low work function metal at a temperature between approximately 200 degrees Celsius and approximately 700 degrees Celsius for less than approximately 60 seconds.