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US 2010/0162262 A1Published application
Split Scheduler
AssigneeApple Inc.
InventorsAndrew J. Beaumont-Smith, Honkai Tam, Daniel C. Murray, John H. Mylius, Peter J. Bannon, Pradeep Kanapathipillai
Life of this patent
Estimating the term…
Abstract
In an embodiment, a scheduler implements a first dependency array that tracks dependencies on instruction operations (ops) within a distance N of a given op and which are short execution latency ops. Other dependencies are tracked in a second dependency array. The first dependency array may evaluate quickly, to support back-to-back issuance of short execution latency ops and their dependent ops. The second array may evaluate more slowly than the first dependency array.
Claims20
A scheduler comprising:
- a first dependency array configured to store a first plurality of dependency indications corresponding to a plurality of instruction operations concurrently storable in the scheduler, wherein a first dependency indication of the first plurality of dependency indications identifies dependencies for a first instruction operation of the plurality of instruction operations on prior instruction operations, the prior instruction operations within N instruction operations of the first instruction operation in program order, where N is an integer greater than or equal to one and less than a number of the plurality of instruction operations, and the prior instruction operations having an execution latency less than or equal to a specified latency;
- a second dependency array configured to store a second plurality of dependency indications corresponding to the plurality of instruction operations, wherein a second dependency indication of the second plurality of dependency indications identifies dependencies for the first instruction operation that are not identified in the first dependency indication;
- and
- a control unit coupled to the first dependency array and the second dependency array, wherein the control unit is configured to schedule the first instruction operation for execution responsive to detecting that the dependencies of the first instruction operation indicated by the first dependency indication and the second dependency indication have been satisfied.
1 more element
A scheduler comprising:
- a first dependency array configured to store a first plurality of dependency indications corresponding to a plurality of instruction operations storable in the scheduler;
- a second dependency array configured to store a second plurality of dependency indications corresponding to the plurality of instruction operations;
- and
- a control unit coupled to the first dependency array and the second dependency array, wherein the control unit is configured to identify one or more instruction operations being scheduled for execution, wherein the first dependency array and the second dependency array are configured to evaluate which instruction operations have satisfied dependencies in the respective first plurality of dependency indications and the second plurality of dependency indications and to indicate the instruction operations as eligible for scheduling to the control unit, wherein the first dependency array is configured to evaluate in less time than the second dependency array.
1 more element
A mapper comprising:
- a rename map configured to store, for each logical register in a processor, an identifier of a most recent update to the logical register and an execution latency indication indicating an execution latency of the instruction operation that performs the most recent update, wherein the rename map is coupled to receive one or more source operand identifiers of a first instruction operation and to output corresponding identifiers and execution latency indications;
- and
- a dependency generation unit configured to generate a first dependency indication and a second dependency indication for the first instruction operation responsive to the identifier and the execution latency corresponding to each source operand identifier, wherein a size of the first dependency indication and the second dependency indication are different.
A processor comprising:
- a mapper coupled to receive a decoded instruction operation and configured to generate a first dependency indication and a second dependency indication for the decoded instruction operation responsive to prior instruction operations in the processor on which the decoded instruction operation depends, wherein the first dependency indication indicates dependencies on prior instruction operations that are within N instruction operations of the decoded instruction operation in program order, and wherein the second dependency vector indicates dependencies on up to M instruction operations, wherein N is an integer greater than or equal to one and less than M, and M is a number of instruction operations concurrently storable in a scheduler;
- and
- the scheduler coupled to the mapper, wherein the scheduler is configured to schedule the decoded instruction operation for execution responsive to evaluating the first dependency vector and the second dependency vector and determining that the dependencies of the decoded instructions have been satisfied.
A method comprising:
- receiving a first instruction operation;
- generating a first dependency indication responsive to prior instruction operations in the processor on which the instruction operation depends, wherein the first dependency indication indicates dependencies on prior instruction operation that are within N instruction operations of the first instruction operation in program order;
- generating a second dependency indication for the first instruction operation, wherein the second dependency vector indicates dependencies on up to M instruction operations, wherein N is an integer greater than or equal to one and less than M, and M is a number of instruction operations concurrently storable in a scheduler;
- writing the first instruction operation and the first and second instruction operation to the scheduler;
- evaluating the first and second dependency indications to determine that dependencies of the first instruction operation have been satisfied;
- and
- scheduling the first instruction operation for execution responsive to determining that dependencies of the first instruction operand and the second instruction operation have been satisfied.
4 more elements
Dependencies are inferred from the claim text.