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US 2010/0162258 A1Published application
Electronic system with core compensation and method of operation thereof
AssigneesSony Corporation, Sony Electronics Inc.
InventorYosuke Muraki
Life of this patent
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Abstract
A method of operation of an electronic system is provided including operating an integrated circuit device having a first core and a second core; detecting a first latency value between the first core and the second core; storing the first latency value in the first core; and compensating for the first latency value in the first core for a first transfer between the first core and the second core.
Claims20
A method of operation of an electronic system comprising:
- operating an integrated circuit device having a first core and a second core;
- detecting a first latency value between the first core and the second core;
- storing the first latency value in the first core;
- and
- compensating for the first latency value in the first core for a first transfer between the first core and the second core.
2 more elements
A method of operation of an electronic system comprising:
- operating an integrated circuit device having a first core and a second core;
- detecting a first latency value between the first core and the second core with the first core;
- storing the first latency value in the first core;
- compensating for the first latency value in the first core for a first transfer between the first core and the second core;
- detecting a second latency value between the second core and the first core;
- storing the second latency value in the second core;
- and
- compensating for the second latency value in the second core for a second transfer between the second core and the first core.
5 more elements
An electronic system comprising:
- an integrated circuit device having a first core and a second core;
- a first latency detect circuit for detecting a first latency value between the first core and the second core;
- a first latency storage for storing the first latency value in the first core;
- and
- a first latency compensator circuit in the first core for compensating the first latency value for a first transfer between the first core and the second core.
2 more elements
Dependencies are inferred from the claim text.