Method for Selectively Enlarging Via and Contact Sizes
AssigneeQi-De Qtan
InventorQi-De Qian
Life of this patent
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Abstract
A method and system for improving the yield of integrated devices is invented by adaptively selecting contact and via sizes. According to this invention, the drawn size of via holes in a design layout is selected based on its neighboring layout geometries. The invention comprises identifying the minimal space required for placing a via; analyzing available free space for potential via size increase; identifying the proximity configuration of the via with other vias on the via layer; selecting an appropriate via size based on the free space and proximity configuration to create an improved design layout; and fabricate the new layout with model based proximity correction such that vias of a plurality of sizes are reproduced on silicon within predetermined tolerances.
Claims20
A computer implemented method for improving the layout of integrated devices, comprising:
- receiving initial layout comprising one or more via layers;
- receiving layout design rules and design objectives associated with said layout;
- generating a partially correct layout solution by increasing the size of a plurality of vias to one or more predetermined target values;
- correcting violations to said design rules and design objectives in said partial solution when such violations are present;
- and
- generating, using a microprocessor, a new layout having a plurality of vias with increased via sizes.
A computer implemented method for improving the layout of integrated devices, comprising:
- receiving initial layout comprising one or more via layers;
- receiving layout design rules and design objectives associated with said layout;
- computing, using a microprocessor, free space associated with said vias under the constraint of said design rules and said design objectives;
- computing sizes of new vias in accordance with said free spaces;
- replacing a plurality of vias in said initial layout with said new vias having said computed sizes.
A computer system for improving the layout of integrated devices, comprising:
- a processor;
- a storage device accessible by said processor for storing layout design rules, initial layout comprising one or more via layers, and design objectives associated with said layout;
- a modified means for via doubling wherein free space associated with a via is made available to said processor for computing via size increases;
- a module for computing the size of new vias in accordance with said free spaces;
- a module for replacing a plurality of vias in said initial layout with said new vias having said computed sizes.
Dependencies are inferred from the claim text.