Method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component features

A portion of a digital integrated circuit, comprising:

• a memory block comprised of a plurality of memory bit-cells;
• and,
• a plurality of logic bricks that perform logic functions;
• wherein said bricks share common geometric patterns, and have sizes and patterns that have been optimized for compatibility with illumination control settings used for the lithography of the memory bit-cells.

A method for designing integrated circuits using regular geometry patterns, the method comprising:

• providing a fabric of regular patterns derived for a particular technology with technology-specific settings, the patterns optimized for compatibility with illumination control settings that will be used for the lithography of memory blocks;
• using the fabric to create logic brick representations;
• and,
• using the fabric to render a compiled a memory block.

A computer-readable medium containing a GDSII representation of an integrated circuit, said GDSII representation including:

• a plurality of logic brick representations;
• and,
• at least one compiled memory block that includes memory cells;
• wherein said plurality of logic brick representations and said compiled memory block consist essentially of geometrical shapes derived from an underlying fabric of regular geometry patterns that have been optimized for compatibility with illumination control settings that will be used for the lithography of the memory cells in the compiled memory block.