Feasibility of ic edits
AssigneeTexas Instruments Incorporated
InventorLance Christopher Jensen
Life of this patent
Estimating the term…
Abstract
One embodiment relates to a computer method of evaluating proposed edits to a target layer of an integrated circuit. In the method, a number of editable regions is determined for metal layers overlying the target layer, where an editable region for a metal layer is laterally arranged between segments of the metal layer. The method identifies a number of possible vertical milling paths that extend from an exterior surface of the integrated surface to the target layer. Each possible vertical milling path passes through at least one editable region. The method generates a number of possible edit plans that are based on both the proposed edits and the number of possible vertical milling paths, where each edit plan places edits in a different combination of possible vertical milling paths.
Claims20
A computer method of evaluating proposed edits to a target layer of an integrated circuit, comprising:
- determining a number of editable regions for metal layers overlying the target layer, where an editable region for a metal layer is laterally arranged between segments of the metal layer;
- identifying a number of possible vertical milling paths extending from an exterior surface of the integrated surface to the target layer, each possible vertical milling path passing through at least one editable region;
- generating a number of possible edit plans that are based on both the proposed edits and the number of possible vertical milling paths, where each edit plan places edits that are based on the proposed edits in a different combination of possible vertical milling paths.
A computer method of evaluating initially proposed edits to a target layer of an integrated circuit, comprising:
- determining a schematic representation for the target layer which includes a number of target layer segments, where a target layer segment is arranged between a pair of branch points from which at least two other target layer segments branch;
- determining a number of possible vertical milling paths extending from an exterior surface of the integrated circuit to the target layer;
- generating a number of possible edit plans by applying the initially proposed edits to the schematic representation in view of the number of possible vertical milling paths, where each edit plan places edits in different possible vertical milling paths.
A computer method of analyzing proposed edits for an integrated circuit, comprising:
- generating a schematic representation of a target layer of the integrated circuit suitable for milling;
- identifying a number of possible vertical milling paths extending from an exterior surface of the integrated surface to the target layer, each possible vertical milling path passing through at least one editable region;
- based on the schematic representation of the target layer, choosing a subset of the number of possible vertical milling paths in which milling is to be carried out.
Dependencies are inferred from the claim text.