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US 2010/0162189 A1Published application
System and method for synthesis reuse
AssigneeCadence Design Systems, Inc.
InventorsLuciano LAVAGNO, Alex KONDRATYEV, Yosinori WATANABE
Life of this patent
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Abstract
A method of synthesis of multiple implementations of a design is provided comprising: translating a model of the design to a first output model compliant with first constraints; and translating the model of the design to a second output model compliant with second constraints.
Claims5
A method of synthesis of multiple implementations of an integrated design, comprising:
- using a synthesis tool to translate a model of the design to output models, each output model compliant with one of a plurality of sets of constraints;
- changing the model of the design so as to produce a changed model of the design;
- and
- using the synthesis tool to translate the changed model of the design to changed output models, each output model compliant with one of the plurality of sets of constraints.
1 more element
A method of synthesis of multiple implementations of an integrated circuit design, comprising:
- providing a model of the design comprising an algorithm implemented by the design;
- providing a first constraint file including at least one first constraint upon implementation of the model;
- inputting the model of the design and the first constraint file to a synthesis tool;
- receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one first constraint;
- providing a second constraint file including at least one second constraint upon implementation of the model;
- inputting the model of the design and the second constraint file to the synthesis tool;
- receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one second constraint;
- changing the model of the design to produce a changed model of the design;
- inputting the changed model of the design and the first constraint file to the synthesis tool;
- and
- receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one first constraint.
8 more elements
A method of synthesis of multiple implementations of an integrated circuit design, comprising:
- providing a model of the design comprising an algorithm implemented by the design;
- providing a first constraint file including at least one first constraint upon implementation of the model;
- inputting the model of the design and the first constraint file to a synthesis tool;
- receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one first constraint;
- providing a second constraint file including at least one second constraint upon implementation of the model;
- inputting the model of the design and the second constraint file to the synthesis tool;
- receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one second constraint;
- changing the model of the design to produce a changed model of the design;
- inputting the changed model of the design and the constraint files to the synthesis tool;
- and
- receiving as output from the synthesis tool an output model of the design for implementing the design to meet both the constraint files.
8 more elements
Dependencies are inferred from the claim text.