Method and system performing block-level rc extraction
AssigneeCadence Design Systems, Inc.
InventorsLi J. SONG, Zhan-Zhong Yao, Rachid Salik, Hao Jl, Taber Smith
Life of this patent
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Abstract
A method, system, and computer program product are disclosed for performing RC extraction from the perspective of the block level. A translation mechanism is employed to convert from a full-chip design domain to a block-level design domain. This allows model-based prediction results to be used in the early design implementation flow when parasitic RC and timing extractions are performed, where the model-based prediction results relate to predictions of manufacturing variations such as thickness and topography.
Claims37
A method for processing electronic design automation information about an electronic design, comprising:
- receiving design information for an electronic design, wherein the design information comprises full-chip design domain information;
- identifying a block within the design information;
- using a processor to translate the full-chip design domain information to block-level design domain information corresponding to the block;
- and
- displaying results of translating the full-chip design domain information to the block-level design domain information on a display device or string the results on a computer readable medium.
A system for processing electronic design automation information about an electronic design, comprising:
- a memory for holding executable program code;
- and
- a processor communicatively coupled to the memory that executes the executable program code for receiving design information for an electronic design, wherein the design information comprises full-chip design domain information, identifying a block within the design information, and using a processor to translate the full-chip design domain information to block-level design domain information corresponding to the block.
A computer program product embodied on a computer usable medium, the computer readable medium having stored thereon a sequence of instructions which, when executed by a processor causes the processor to execute a method for processing electronic design automation information about an electronic design, the method comprising:
- receiving design information for an electronic design, wherein the design information comprises full-chip design domain information;
- identifying a block within the design information;
- using a processor to translate the full-chip design domain information to block-level design domain information corresponding to the block;
- and
- displaying results of translating the full-chip design domain information to the block-level design domain information on a display device or string the results on a computer readable medium.
Dependencies are inferred from the claim text.