# US 2010/0162187 A1 · Mixed-Height High Speed Reduced Area Cell Library > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2010/0162187 A1 - Document ID: US20100162187A1 - Status: Published application - Kind: A1 - Application number: 12/370,065 - Filed: 2009-02-12 - Published: 2010-06-24 - Earliest claimed: 2008-12-23 - Assignees: Broadcom Corporation - Inventors: Paul Penzes; Koen Lampaert - Web page: https://patentgrep.com/patent/US20100162187A1 ## CPC - G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) - H10D 84/907: {CMOS gate arrays} - H10D 89/10: Integrated device layouts - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A mixed-height cell library for designing integrated circuits is provided. The mixed-height cell library includes a first plurality of cells having a first track height and a second plurality of cells having a second track height that are configured to be coupled to the first plurality of cells at respective power and ground rail lines. A method for mixed-height cell placement and optimization is also provided. The method comprises abutting cells of different track heights to form a plurality of rows of cells by coupling power and ground rails of the cells at a secondary layer that is different from a primary layer that is used to connect active material and determining whether re-ordering cells within rows allows for further compaction of adjacent rows. The method further comprises re-ordering cells within rows so to allow for further compaction of adjacent rows. The method also includes the steps of splitting rows vertically to minimize the distance between the split rows. ## Claims ### Claim 1 A method for optimizing a physical layout of a circuit formed using cells of different track heights, comprising: selecting a plurality of cells necessary to construct the circuit, wherein two or more cells in the plurality of cells have different track heights; joining the plurality of cells to form the circuit by coupling power and ground rails of the cells at a secondary layer that is different from a primary layer that is used to connect active material; and compacting adjacent rows so as to minimize distance between rows within design rules check constraints. ### Claim 2 (depends on 1) The method of claim 1, further comprising forming the plurality of cells such that the distance between power and rail lines for a cell with a higher track height is the same as the distance between power and rail lines of for a cell with a lower track height. ### Claim 3 (depends on 1) The method of claim 1, further comprising forming the plurality of cells such that a drive strength of cells with a higher track height is greater than a drive strength of cells with a shorter track height. ### Claim 4 (depends on 1) The method of claim 1, further comprising forming the plurality of cells such that a leakage power of cells with a higher track height is greater than a leakage power of cells with a shorter track height. ### Claim 5 (depends on 1) The method of claim 1, further comprising forming the plurality of cells such that a first plurality of cells of a first track height includes a first set of logic functions. ### Claim 6 (depends on 5) The method of claim 5, further comprising forming the plurality of cells such that a second plurality of cells of a second track height includes a corresponding second set of logic functions that are equivalent in logic to the first set of logic functions and have a greater drive strength and leakage power compared to the corresponding first plurality of cells. ### Claim 7 A method for optimizing placement in a physical layout of a circuit formed using cells of different track heights, comprising: selecting a plurality of cells necessary to construct the circuit, wherein two or more cells in the plurality of cells have different track heights; forming a plurality of rows by joining the plurality of selected cells, wherein adjacent cells are joined by coupling power and ground rails of the adjacent cells at a secondary layer that is different from a primary layer that is used to connect active material; minimizing a distance between adjacent rows; re-ordering cells within one or more rows, wherein the cells within a row are re-ordered to minimize the vertical distance between adjacent rows; adjusting routing to compensate for re-ordered cells; and minimizing a distance between rows by compacting rows. ### Claim 8 A method for optimizing placement in a physical layout of a circuit formed using cells of different track heights, comprising: selecting a plurality of cells necessary to construct the circuit, wherein two or more cells in the plurality of cells have different track heights; forming a plurality of rows by joining the plurality of selected cells, wherein adjacent cells are joined by coupling power and ground rails of the cells at a secondary layer that is different from a primary layer that is used to connect active material; vertically splitting one or more rows to form split rows to enable minimizing a distance between adjacent rows that have cells of the same track height; minimizing a distance between adjacent split rows that have cells of the same track height; re-ordering cells within one or more split rows that have cells of different track heights to form re-ordered split rows and to enable further minimization of the vertical distance between adjacent split rows; adjusting routing in the re-ordered split rows to compensate for re-ordered cells; and minimizing a distance between the re-ordered split rows by compacting the re-ordered split rows. ### Claim 9 A mixed-height cell library for designing a circuit, comprising: a first plurality of cells having a first track height; a second plurality of cells having a second track height and configured to be coupled to the first plurality of cells at respective power and ground rail lines; wherein the first and second plurality of cells are configured to be coupled at respective power and ground rail lines at a secondary layer that is different from a primary layer that is used to connect active material. ### Claim 10 (depends on 9) The mixed-height cell library of claim 9, wherein a drive strength of cells with a higher track height is greater than a drive strength of cells with a shorter track height. ### Claim 11 (depends on 9) The mixed-height cell library of claim 9, wherein a leakage power of cells with a higher track height is greater than a leakage power of cells with a shorter track height.