Apparatus and method for coding qc-ldpc code
AssigneeElectronics and Telecommunications Research Institute
InventorsJong-Ee OH, Minho CHEONG, Yu-Ro LEE, Sok-Kyu LEE, Yongho LEE
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AssigneeElectronics and Telecommunications Research Institute
InventorsJong-Ee OH, Minho CHEONG, Yu-Ro LEE, Sok-Kyu LEE, Yongho LEE
Estimating the term…
A high-speed quasi-cyclic low density parity check (QC-LDPC) coding apparatus for coding inputted information into a generator matrix having a dual diagonal matrix format includes: a parity bit generation unit configured to generate an arbitrary parity bit; a temporary parity bit generation unit configured to constitute the inputted information with circulants, and shift and combine the respective circulants at each row to generate a temporary parity bit; a corrected bit generation unit configured to generate corrected bits of parity bits by using an output of the temporary parity bit generation unit; and a parity bit correction unit configured to correct the temporary parity bit by reflecting an output of the corrected bit generation unit to the output of the temporary parity bit generation unit.
A high-speed quasi-cyclic low density parity check (QC-LDPC) coding apparatus for coding inputted information into a generator matrix having a dual diagonal matrix format, the QC-LDPC coding apparatus comprising:
A high-speed quasi-cyclic low density parity check (QC-LDPC) coding method for coding inputted information into a generator matrix having a dual diagonal matrix format, the QC-LDPC coding method comprising:
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