Circuits for implementing parity computation in a parallel architecture ldpc decoder

In a parallel pipelined low density parity check (LDPC) circuit having a plurality of bit units and having a plurality of parity units controllably coupled with the plurality of bit nodes and having a controller for sequencing operation of the bit nodes and operation of the parity units for exchanging bit messages, the LDPC decoder operable to perform an iterative, message passing, min sum algorithm, each parity unit comprising:

• a memory logic block adapted to store data relating to parity check computation of the parity unit circuit, the memory logic block adapted to receive a next bit message (bit_mes) from each bit node the participates in the parity computation of the parity unit;
• a first computational logic block coupled to the memory logic block, adapted to retrieve data from the memory logic block and adapted to compute a parity message (par_mes) and a corresponding sign (par_sign) of the parity message and adapted to output the parity message and the corresponding sign for application to a bit node under control of the controller;
• and
• a second computational logic block coupled to the memory logic block, adapted to retrieve data from the memory logic block and adapted to compute new values for the retrieved data and adapted to store the new values in the memory logic block, the second computational logic block adapted to receive a next bit message (bit_mes) from the bit node and adapted to receive a sign of the bit message (bit_sign) from said each bit node that participates in the parity computation of the parity unit and adapted to receive a hard decision value (bit_hard) from said each bit node.