Memory device
AssigneeKabushiki Kaisha Toshiba
InventorHaruki TODA
Life of this patent
Estimating the term…
Abstract
A memory device including: a memory cell array; an error-detecting and correcting circuit; and a buffer register disposed for temporally storing write and read data. Write data loaded in the buffer register are encoded in the error-detecting and correcting circuit to be over-written in the buffer register together with check bits, and then transferred to be written into the cell array. Read data read from the cell array and held in the buffer register together with check bits are decoded in the error-detecting and correcting circuit to be corrected, over-written in the buffer register and then output.
Claims20
A memory device comprising:
- a memory cell array;
- an error-detecting and correcting circuit configured to detect and correct errors contained in read data read from the memory cell array;
- and
- a buffer register disposed for temporally storing write data to be written into the memory cell array and read data read from the memory cell array, wherein
- write data loaded in the buffer register are encoded in the error-detecting and correcting circuit to be over-written in the buffer register together with check bits, and then transferred to and written into the memory cell array, and
- read data read from the memory cell array and held in the buffer register together with check bits are decoded in the error-detecting and correcting circuit to be corrected, over-written in the buffer register and then output to the external.
A memory device comprising:
- a memory cell array;
- an error-detecting and correcting circuit configured to detect and correct errors contained in read data read from the memory cell array;
- and
- two systems of buffer registers disposed for temporally storing write or read data, wherein
- the memory device has an external data transfer mode, in which read or write data are alternately burst-transferred with the two systems of the buffer registers, and wherein
- within a burst cycle in one of the buffer registers, an internal data transfer mode including write data transfer and read data transfer is performed between the other buffer register and the memory cell array.
Dependencies are inferred from the claim text.