Memory scrubbing in third dimension memory
AssigneeUnity Semiconductor Corporation
InventorRobert Norman
Life of this patent
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AssigneeUnity Semiconductor Corporation
InventorRobert Norman
Estimating the term…
A method for memory scrubbing is provided. In this method, a first resistance of a reference memory element is read. A second resistance of a memory element also is read. A difference between the first resistance and the second resistance is sensed and a programming error associated with the second resistance is detected based on the difference. Each memory element is non-volatile and re-writeable, and can be positioned in a two-terminal memory cell that is one of a plurality of memory cells positioned in a two-terminal cross-point memory array. Active circuitry for performing the memory scrubbing can be fabricated FEOL in a logic layer and one or more layers of the two-terminal cross-point memory arrays can be fabricated BEOL over the logic layer. Each memory cell can optionally include non-ohmic device (NOD) electrically in series with the memory element and the two terminals of the memory cell.
A method for scrubbing memory, comprising:
A third dimension memory system, comprising:
A read and error detection circuit for scrubbing memory, comprising:
A read and error detection circuit for scrubbing memory, comprising:
A method for memory scrubbing, comprising:
A method for scrubbing memory, comprising:
Dependencies are inferred from the claim text.