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US 2010/0162066 A1Published application
Acceleration of header and data error checking via simultaneous execution of multi-level protocol algorithms
OwnerVeera Papirla, David A. Danielinventors
Life of this patent
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Abstract
An error detection system and methodology where the undesirable consequence of encapsulation (additional latency or delay) for virtualization applications such as i-PCI or iSCSI is minimized for the vast majority of data transactions. Cyclic Redundancy Checks (CRCs) and checksums are executed simultaneously in parallel, immediately on reception of a data packet regardless of the relative processing order in relation to the OSI model.
Claims22
A device, comprising;
- a module configured to perform error checking on a data packet processed by a plurality of protocol blocks in a description framework of a computer network protocol, wherein the error checking is configured to be disassociated from the protocol blocks.
Dependencies are inferred from the claim text.