Dft technique to apply a variable scan clock including a scan clock modifier on an ic

A method of providing a variable scan clock for a test block, comprising:

• receiving a test scan clock signal from test equipment at a scan clock modifier of an integrated circuit, said test scan clock signal having a fixed frequency for a test block;
• receiving clock control signals from said test equipment at said scan clock modifier;
• and
• providing a scan clock signal at an output of said scan clock modifier to drive a scan chain for said test block, wherein said scan clock signal varies based on values of said clock control signals.

An integrated circuit, comprising:

• a test interface configured to receive a test scan clock signal, test data and test control signals, including clock control signals, from test equipment;
• at least one scan chain coupled to said test interface;
• and
• a scan clock modifier, coupled between said test interface and said at least one scan chain, configured to modify said test scan clock signal to provide a scan clock signal that varies based on values of said clock control signals, said scan clock signal provided to drive said at least one scan chain.

A scan clock modifier located on an integrated circuit and coupled between a test interface and at least one scan chain of said integrated circuit, said scan clock modifier comprising:

• a first AND gate having an output, an input coupled to said test interface for receiving a test scan clock signal and an input coupled to a first clock control line;
• a second AND gate having an output, an input for receiving a modified test scan clock signal and an input coupled to a second clock control line;
• and
• an OR gate having an output, one input coupled to said first AND gate output, a second input coupled to said second AND gate output, and a third input coupled to a third clock control line, said OR gate configured to provide a scan clock signal at said output thereof for said at least one scan chain and in response to values on said first, second and third clock control lines.

A library of standard logic elements, comprising:

• a standard logic element corresponding to a scan clock modifier, including:
• logic circuitry configured to provide at least one selected clock signal based on a test scan clock signal and a first clock control signal, both of said test scan clock signal and said first clock control signal received from test equipment;
• and
• comparison logic configured to provide a scan clock signal based on said at least one selected clock signal and at least one other clock control signal received from said test equipment, wherein said first and said at least one other clock control signals are different clock control signals.