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US 2010/0162059 A1Published application
Core circuit test architecture
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
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Abstract
A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths. Select and enable signals control the operation of the scan path sections. The output of each scan path passes through a multiplexer to compare circuits on the semiconductor substrate. The compare circuits also receive expected data and mask data. The compare circuits provide a fail flag output from the semiconductor substrate.
Claims3
A semiconductor integrated circuit comprising:
- A. a substrate of semiconductor material;
- B. a stimulus bus of leads formed in the substrate;
- C. a response bus of leads formed in the substrate;
- D. a first multiplexer formed in the substrate having first and second inputs and an output, the second input being connected to the stimulus bus of leads;
- E. a second multiplexer formed in the substrate having first and second inputs and an output, the output being connected to the response bus of leads;
- and
- D. a serial scan path formed in the substrate, the scan path being formed of plural flip-flops connected in series, the scan path including a first section and a second section selectively connected in series, each section having a serial input and a serial output, the serial input of the first section being connected to the stimulus bus of leads, the serial output of the first section being connected to the first input of the first multiplexer and the first input of the second multiplexer, the serial input of the second section being connected to the output of the first multiplexer and the serial output of the second section being connected to the second input of the second multiplexer.
4 more elements
Dependencies are inferred from the claim text.