Sequential element low power scan implementation
AssigneeLSI Corporation
InventorsJeff S. Brown, Mark F. Turner, Jonathan Byrn
Life of this patent
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Abstract
Disclosed herein is a sequential element having a master stage and a slave stage and a method of testing an IC having a scan chain and an IC. In one embodiment, the sequential element includes: (1) an input scan multiplexor configured to place the sequential element in a functional mode or a scan mode in response to a scan enable input and (2) a scan out driver coupled to the slave stage and configured to provide a scan out signal when the sequential element is in the scan mode, the scan out driver coupled to an inverted scan enable input for a negative voltage supply.
Claims22
A sequential element having a master stage and a slave stage, comprising:
- an input scan multiplexer configured to place said sequential element in a functional mode or a scan mode in response to a scan enable input;
- and
- a scan out driver coupled to said slave stage and configured to provide a scan out signal when said sequential element is in said scan mode, said scan out driver coupled to an inverted scan enable input for a negative voltage supply.
A method of testing an integrated circuit having a scan chain, comprising:
- asserting a scan enable input coupled to sequential elements of said scan chain;
- receiving a scan input at said scan chain;
- and
- providing a scan output at a scan out driver of a sequential element of said scan chain, said scan out driver coupled to an inverted scan enable input for a negative voltage supply.
An integrated circuit, comprising:
- functional circuitry;
- and
- at least one scan chain coupled to said functional circuitry, said scan chain having at least one sequential element having a master stage and a slave stage, said sequential element including:
- an input scan multiplexor configured to place said sequential element in a functional mode or a scan mode in response to a scan enable input;
- and
- a scan out driver coupled to said slave stage and configured to provide a scan out signal when said sequential element is in said scan mode, said scan out driver coupled to an inverted scan enable input for a negative voltage supply.
A library of standard logic elements, comprising:
- a standard logic element corresponding to a sequential element having a master stage and a slave stage, and including:
- an input scan multiplexor configured to place said sequential element in a functional mode or a scan mode in response to a scan enable input;
- and
- a scan out driver coupled to said slave stage and configured to provide a scan out signal when said sequential element is in said scan mode, said scan out driver coupled to an inverted scan enable input for a negative voltage supply.
A sequential element having a master stage and a slave stage, comprising:
- an input scan multiplexer configured to place said sequential element in a functional mode or a scan mode in response to a scan enable input;
- and
- a scan out driver coupled to said slave stage and configured to provide a scan out signal when said sequential element is in said scan mode, said scan out driver coupled to said scan enable input for a positive voltage supply.
Dependencies are inferred from the claim text.