US 2010/0162056 A1 · SEMICONDUCTOR DEVICE

Abstract

A semiconductor device includes a CPU, a memory, a memory BIST circuit, a first selector that selects and outputs an address and control signal from the memory BIST circuit, when performing a test using the memory BIST circuit, and selects and outputs an address and control signal of the CPU when not performing a test using the memory BIST circuit, a second selector that selects and outputs write data from the memory BIST circuit when performing a test using the memory BIST circuit, and selects and outputs write data of the CPU when not performing a test using the memory BIST circuit, a first flip-flop that samples an output of the first selector (11) and a second flip-flop that samples an output of the second selector. An address and control signal and write data output from the first and second flip-flops are supplied to an address and control terminal and a write data terminal of the memory.

Claims6

Dependent claims

A semiconductor device comprising:

a memory;
a memory BIST (Built-In Self-Test) circuit that performs a test of the memory;
and
a CPU (Central Processing Unit) that includes:
a flip-flop that receives and samples a signal for accessing the memory to output the sampled signal for supply to the memory;
and
a selector arranged at a stage preceding to the flip-flop, the selector receiving a signal for accessing the memory output from the memory BIST circuit and a signal for accessing the memory generated by the CPU and selecting one of the signals received, the signal selected by the selector being supplied to the flip-flop.

4 more elements

Dependencies are inferred from the claim text.

Semiconductor device

Life of this patent

Semiconductor device

Life of this patent

Abstract

Claims6