Memory system, transfer controller, and memory control method
AssigneeKabushiki Kaisha Toshiba
InventorsTakeo Morita, Akira Aoki, Tetsuya Murakami
Life of this patent
Estimating the term…
Abstract
A memory system includes a nonvolatile memory, a volatile buffer memory connected to the nonvolatile memory, an error counting unit that detects, for each of divided areas formed by dividing a storage area of the volatile buffer memory into a plurality of areas, a parity error in inputting data to and outputting data from the divided areas and counts a number of times of accumulation of the parity error, and a control unit that sets the divided area, in which the number of times of accumulation of the parity error counted by the error counting unit exceeds a predetermined number of times, in a disabled state.
Claims21
A memory system comprising:
- a nonvolatile memory;
- a volatile buffer memory connected to the nonvolatile memory;
- an error counting unit that detects, for each of divided areas formed by dividing a storage area of the volatile buffer memory into a plurality of areas, a parity error in inputting data to and outputting data from the divided areas and counts a number of times of accumulation of the parity error;
- and
- a control unit that sets the divided area, in which the number of times of accumulation of the parity error counted by the error counting unit exceeds a predetermined number of times, in a disabled state.
A transfer controller that controls a nonvolatile memory and a volatile buffer memory connected to the nonvolatile memory, the transfer controller comprising:
- an error counting unit that detects, for each of divided areas formed by dividing a storage area of the volatile buffer memory into a plurality of areas, a parity error in inputting data to and outputting data from the divided areas and counts a number of times of accumulation of the parity error;
- and
- a control unit that sets the divided area, in which the number of times of accumulation of the parity error counted by the error counting unit exceeds a predetermined number of times, in a disabled state.
A memory control method for controlling a nonvolatile memory and a volatile buffer memory connected to the nonvolatile memory, the memory control method comprising:
- dividing a storage area of the volatile buffer memory into a plurality of areas;
- detecting a parity error in inputting data to and outputting data from the divided areas;
- counting a number of times of accumulation of the parity error;
- and
- setting the divided area, in which the number of times of accumulation of the parity error exceeds a predetermined number of times, in a disabled state.
Dependencies are inferred from the claim text.