Error detection method and a system including one or more memory devices
AssigneeMosaid Technologies Incorporated
InventorPeter Gillingham
Life of this patent
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Abstract
A system including one or more memory devices, and an error detection and correction method are disclosed. A memory device of the system includes an input for receiving a packet. A first portion of the packet may include at least one command byte, and a second portion of the packet may include parity bits to facilitate command error detection. The memory device may include an error manager configured to detect, based on the parity bits, whether an error exists in the at least one command byte, and circuitry configured to provide the packet to the error manager.
Claims28
A memory device comprising:
- an input for receiving a packet, a first portion of the packet comprising at least one command byte, and a second portion of the packet including parity bits to facilitate command error detection;
- an error manager configured to detect, based on the parity bits, whether an error exists in the at least one command byte;
- and
- circuitry configured to provide the packet to the error manager.
A system comprising:
- a plurality of semiconductor memory devices;
- and
- a controller device for communicating with the devices, said controller comprising:
- a command engine for generating a memory device-destined packet, a first portion of the packet comprising at least one command byte, and a second portion of the packet including parity bits to facilitate command error detection;
- and
- an output capable of outputting the packet to a first device of the plurality of semiconductor memory devices, and
- a series-interconnection configuration existing between the controller device and the semiconductor memory devices of the system, wherein the system has a point-to-point ring topology.
A method carried out within a memory device having an input for receiving a packet, the method comprising:
- receiving the packet, a first portion of the packet comprising at least one command byte, and a second portion of the packet including parity bits to facilitate command error detection;
- and
- detecting, based on the parity bits, whether an error exists in the at least one command byte.
Dependencies are inferred from the claim text.