Power Management of a Spare DRAM on a Buffered DIMM by Issuing a Power On/Off Command to the DRAM Device

A computer memory, comprising:

• one or more of a semiconductor memory device having an internal memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns, and
• a memory module rank of such memory devices arranged in an array of one or more of said semiconductor memory device on a substrate which can be coupled via a memory device data interface to a memory system as a memory subsystem,
• each of said memory devices having a power-off state where an individual device can be placed into a power-off state.

A computer memory, comprising:

• one or more of a semiconductor memory device having an internal memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns, and
• a memory module rank of such memory devices arranged in an array of one or more of said semiconductor memory device on a substrate which can be coupled via a memory device data interface to a memory system as a memory subsystem,
• each of said memory device having a low power shut-down state that can be activated using a common memory interface.

A method for control of a computer memory, comprising an internal memory array having a plurality of semiconductor dynamic random access memory (DRAM) cells arranged in a matrix of rows and columns, said method comprising issuing to a DRAM power control comprising a command decoder which provides a power-state program signal and a power-state reset signal as a power-state control command to control the power state of said DRAM.

A method for control of a computer memory, having a rank of plurality of an internal memory cell array memory devices (DRAMs) each having a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns, and a local hub device, said method comprising issuing to a DRAM power control comprising a command decoder which provides a power-state program signal and a power-state reset signal, one of two commands, either normal mode command or a power-state programming mode command to control the power state of said DRAM, whereby during operation any failing and/or replaced memory device(s) of the memory cell array are placed in a low power state once they are replaced by a spare memory device.