Back to results
US 2010/0161948 A1Published application
Apparatus and Method for Processing Complex Instruction Formats in a Multi-Threaded Architecture Supporting Various Context Switch Modes and Virtualization Schemes
AssigneeSoft Machines, Inc.
InventorMohammad A. Abdallah
Life of this patent
Estimating the term…
Abstract
A unified architecture for dynamic generation, execution, synchronization and parallelization of complex instructions formats includes a virtual register file, register cache and register file hierarchy. A self-generating and synchronizing dynamic and static threading architecture provides efficient context switching.
Claims10
A multiple thread architecture, comprising:
- a plurality of thread registers storing a corresponding plurality of thread contexts;
- and
- inter-thread communication circuitry between the plurality of thread registers to support thread communication and synchronization.
A multiple thread architecture, comprising:
- a set of registers;
- a set of execution units;
- circuitry to coordinate the set of registers and set of execution units to support instruction level parallelism and the execution of software threads and hardware generated threads.
A multiple thread architecture, comprising:
- a set of register files configurable to include context identification without designating a separate register file for each context.
A multiple thread architecture, comprising:
- an execution bucket;
- and
- a register file hierarchy configured to support high bandwidth small capacity register files adjacent the execution bucket and lower bandwidth and larger capacity register files removed from the execution bucket.
A context switch architecture, comprising:
- context switch circuitry to support the capture of current state information;
- and
- a context storage mechanism configured to simultaneously store a portion of the current state information and a portion of previous state information, so as to incrementally switch context.
A multiple thread architecture, comprising:
- a plurality of thread registers storing a corresponding plurality of thread contexts;
- and
- inter-thread communication circuitry between the plurality of thread registers to support thread communication and synchronization.
Dependencies are inferred from the claim text.