Information handling system with real and virtual load/store instruction issue queue

A processor, comprising:

• a fetch unit that fetches a plurality of instruction threads, the instruction threads including load/store instructions;
• a decode unit, coupled to the fetch unit, that decodes, the load/store instructions;
• a dispatch unit, coupled to the decode unit, that dispatches the load/store instructions;
• an issue queue, coupled to the dispatch unit, wherein the dispatch unit dispatches each of the load/store instructions to the issue queue depending on availability of space in the issue queue, the issue queue designating each of the load/store instructions in the issue queue as being a real load/store instruction or a virtual load/store instruction via a respective real/virtual indicator for each load/store instruction;
• and
• a load/store unit, coupled to the issue queue, that executes load/store instructions issued by the issue queue.

An information handling system (IHS), comprising:

• a memory;
• a processor, coupled to the memory, the processor including:
• a fetch unit that fetches a plurality of instruction threads from the memory, the instruction threads including load/store instructions;
• a decode unit, coupled to the fetch unit, that decodes, the load/store instructions;
• a dispatch unit, coupled to the decode unit, that dispatches the load/store instructions;
• an issue queue, coupled to the dispatch unit, wherein the dispatch unit dispatches each of the load/store instructions to the issue queue depending on availability of space in the issue queue, the issue queue designating each of the load/store instructions in the issue queue as being a real load/store instruction or a virtual load/store instruction via a respective real/virtual indicator for each load/store instruction;
• and
• a load/store unit, coupled to the issue queue, that execute load/store instructions issued by the issue queue.