Third dimensional memory with compress engine

An integrated circuit, comprising:

• a substrate including active circuitry fabricated on the substrate;
• a third dimensional memory array in contact with and fabricated directly above the substrate and including a memory layer, wherein the memory layer is configured to store an input independent of storing a compressed copy of the input;
• a processor included in the active circuitry and configured to transform the input to form a compressed data;
• and
• a controller included in the active circuitry and configured to control a request from the processor to access the third dimensional memory array;
• a port circuit included in the active circuitry and configured to provide a plurality of access ports to the third dimensional memory array;
• a priority circuit included in the active circuitry and configured to resolve multiple requests from the port circuit to access the third dimensional memory array;
• and
• a processor memory included in a portion of the third dimensional memory array, the portion of the third dimensional memory array being configured to store data used by the processor.

A method, comprising:

• receiving an input independent of another input;
• storing the input into a third dimensional memory array fabricated directly on top of a substrate that includes active circuitry fabricated on the substrate;
• locating the input in the third dimensional memory array using a scatter-gather circuit included in the active circuitry;
• compressing the input to form a compressed copy of the input;
• and
• replacing the input with the compressed copy of the input.