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US 2010/0161905 A1Published application
Latency Reduction for Cache Coherent Bus-Based Cache
AssigneeApple Inc.
InventorsBrian P. Lilly, Sridhar P. Subramanian, Ramesh Gunna
Life of this patent
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AssigneeApple Inc.
InventorsBrian P. Lilly, Sridhar P. Subramanian, Ramesh Gunna
Estimating the term…
In one embodiment, a system comprises a plurality of agents coupled to an interconnect and a cache coupled to the interconnect. The plurality of agents are configured to cache data. A first agent of the plurality of agents is configured to initiate a transaction on the interconnect by transmitting a memory request, and other agents of the plurality of agents are configured to snoop the memory request from the interconnect. The other agents provide a response in a response phase of the transaction on the interconnect. The cache is configured to detect a hit for the memory request and to provide data for the transaction to the first agent prior to the response phase and independent of the response.
A system comprising:
A cache comprising a cache memory configured to store cache blocks and circuitry coupled to receive a memory request, wherein the cache is configured to speculatively arbitrate for a data interconnect to transfer data corresponding to the memory request prior to detecting whether or not the memory request is a hit in the cache memory, wherein the data interconnect is used by a plurality of agents to transfer data among the plurality of agents and the cache, and wherein the cache is configured to initiate a data transfer on the data interconnect responsive to receiving a grant of the data interconnect for the speculative arbitration and further in response to detecting a hit for the memory request.
A method comprising:
A cache coupled to receive an address phase of a transaction on an interconnect, wherein the cache is configured to detect a cache hit for the transaction, and wherein the cache is configured to transmit a first cache hit response prior to a response phase of the transaction on the interconnect to indicate the cache hit, and wherein the cache is further configured to transmit a second cache hit response on the interconnect during the response phase of the transaction.
Dependencies are inferred from the claim text.