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US 2010/0161892 A1Published application
Pseudo dual-ported sram
AssigneeFulcrum Microsystems, Inc.
InventorsJonathan Dama, Andrew Lines
Life of this patent
Estimating the term…
Abstract
A memory is described which includes a main memory array made up of multiple single-ported memory banks connected by parallel read and write buses, and a sideband memory equivalent to a single dual-ported memory bank. Control logic and tags state facilitates a pattern of access to the main memory and the sideband memory such that the memory performs like a fully provisioned dual-ported memory capable of reading and writing any two arbitrary addresses on the same cycle.
Claims10
A memory, comprising:
- a main memory comprising a plurality of single-ported memory banks, each memory bank comprising a first number of entries;
- parallel busses configured to enable simultaneous writing and reading from different ones of the single-ported memory banks;
- a sideband memory comprising the first number of entries, each of the entries in the sideband memory mapping to a corresponding one of the entries in one of the memory banks in the main memory, the sideband memory being configured to allow parallel read and write accesses to the sideband memory per cycle;
- switching circuitry configured to direct read and write operations to either the main memory or the sideband memory;
- and
- control logic configured to track to which of the memory banks in the main memory each of the entries in the sideband memory corresponds, and to deterministically control the switching circuitry in response to memory address information to effect a pattern of access to the main memory and the sideband memory such that the memory performs like a fully provisioned dual-ported memory.
3 more elements
A shared-memory switch, comprising:
- a plurality of receive ports;
- a plurality of transmit ports;
- a memory comprising:
- a main memory comprising a plurality of single-ported memory banks, each memory bank comprising a first number of entries;
- parallel busses configured to enable simultaneous writing and reading from different ones of the single-ported memory banks;
- a sideband memory comprising the first number of entries, each of the entries in the sideband memory mapping to a corresponding one of the entries in one of the memory banks in the main memory, the sideband memory being configured to allow parallel read and write accesses to the sideband memory per cycle;
- switching circuitry configured to direct read and write operations to either the main memory or the sideband memory;
- and
- control logic configured to track to which of the memory banks in the main memory each of the entries in the sideband memory corresponds, and to deterministically control the switching circuitry in response to memory address information to effect a pattern of access to the main memory and the sideband memory such that the memory performs like a fully provisioned dual-ported memory;
- receive crossbar circuitry operable to connect any of the receive ports with the memory;
- transmit crossbar circuitry operable to connect the memory with any of the transmit ports;
- and
- switching logic which is operable to control interaction of the ports, crossbar circuitry, and memory to effect storage and retrieval of data in the memory.
10 more elements
Dependencies are inferred from the claim text.