Architecture for Address Mapping of Managed Non-Volatile Memory

A non-volatile memory (NVM) package, comprising:

• an interface operable for receiving a block address and a first chip enable signal from a host processor coupled to the interface;
• a plurality of concurrent access units each containing a plurality of blocks;
• and
• a processor coupled to the interface and the plurality of concurrently addressable units, where in response to the chip enable signal from the host processor, the processor activates a first concurrently addressable unit using a first internal chip select enable signal, activating a second concurrently addressable unit using a second, internal chip select enable signal, mapping the block address to blocks in the activated first and second concurrently addressable units, and executing a sequence of commands for concurrently performing read or write operations on the blocks in the activated first and second currently addressable units.

A method performed by host processor coupled to a non-volatile memory (NVM) package, comprising:

• sending a request for parameters to the NVM package, the NVM package including a plurality of concurrently addressable units;
• responsive to the request, receiving a run parameter and a stride parameter, where the run parameter indicates a number of concurrently addressable units in the NVM package that are accessible using a single chip enable signal provided by the host processor, and where the stride parameter indicates a number of blocks for an operation command within a concurrently addressable unit;
• and
• sending a sequence of commands to the NVM package for concurrently performing atomic transactions on one or more concurrently addressable units, the sequence of commands include an address generated by the host processor based on the run and stride parameters.

A method performed by an embedded non-volatile memory device, comprising:

• receiving commands from a host controller requesting operations on non-volatile memory;
• storing the commands in a queue of the non-volatile memory device;
• and
• reordering the commands in the queue in response to a trigger event.

A method performed by en embedded non-volatile memory device, comprising:

• receiving read commands from a host controller requesting read operations on non-volatile memory;
• storing the read commands in a first queue;
• receiving program commands from the host controller requesting program operations on the non-volatile memory;
• storing the program commands in a second queue;
• receiving erase commands from the host controller requesting erase operations on the non-volatile memory
• storing the erase commands in a third queue;
• and
• reordering one or more of the read, program or erase commands in their respective queues.